aDVANCED TECHNICAL PROGRAM

LATW2012 Preliminary Technical Program in PDF

 

13th Latin American Test Workshop
PRELIMINARY TECHNICAL PROGRAM

Wednesday, April 11th 2012

08:30 – 09:00   TTEP Tutorials and LATW Registration

09:00 – 09:20   LATW Opening Session

9:20 – 10:10   KEYNOTE ADDRESS: On-Chip Structures for Parametric Test
Presenter: Jacob Abraham, University of Texas at Austin, USA

10:10 – 10:40    Coffee break

10:40 – 11:40    SESSION 1: Fault Analysis, Simulation and Diagnosis
Session Chair: Fabian Vargas, Catholic University of Rio Grande do Sul (PUCRS), Brazil

Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
Alejandro Cook, Michael Imhof, Abdullah Mumtaz, Hans-Joachim Wunderlich – University of stuttgart,
Sybille Hellebrand – University of paderborn

Simulation of SET Faults in a Voltage Controlled Oscillator
Walter Calienes bartra, Fernanda Kastensmidt, Ricardo Reis – Ufrgs

Low Voltage Testing for Interconnect Opens under Process Variations
Jesus Moreno, Victor Champac – Inaoe, Michel Renovell – universite de montpellier II

11:40 – 12:20   SPECIAL SESSION 1: Robust and Testable Designs in the Nano-Regime
Organizer: Kaushik Roy, Purdue University, USA   

Low-Power Design under variation using error prevention and error tolerance
Kwanyeob Chae, Saibal Mukhopadhayay – georgia Institute of technology

Variation-aware and self–healing design methodology for a system-on-chip
Jangjoon Lee, Srikar Bhaggavatula, Kaushik Roy, Byunghoo Jung – purdue university

12:20 – 14:00   Lunch and TTEP Registrations

14:00 – 15:30   Test Technology Educational Program (TTEP)

TTEP 1:         Statistical Adaptive Test Methods Targeting “Zero Defect” IC Quality and Reliability
Presenter:      Adit D. Singh, Auburn University, USA
Email:            adsingh@auburn.edu

15:30 – 16:00   Coffee break

16:00 – 17:30 Test Technology Educational Program (TTEP)

TTEP 2:          Design for Yield and Reliability
Presenter:      Yervant Zorian, Synopsys, USA
Email:            Yervant.Zorian@synopsys.com

20:30 – 22:00   Welcome Reception

 

Thursday, April 12th 2012

09:00 – 09:30   INVITED TALK: Designing RFID Chips for Test & Security: Towards a Reliable Internet of Things
Presenter: Marcelo Lubaszewski, CEITEC S.A., Brazil

09:30 – 10:30   SESSION 2: Design Verification and Validation 
Session Chair: Florence Azais, LIRMM, France

Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis
Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar – tallinn university of technology

A Guiding Heuristic for the Semi-Formal Verification of High-Level Designs
Alair Dias Junior, Diógenes Silva Junior – federal university of minas gerais

Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification
Edgar Romero, Marius Strum, Jiang Chau Wang – University of sao paulo

10:30 – 10:50   Coffee break

10:50 – 11:30   SESSION 3: Design Optimization
Session Chair: Franciso Russi, Synopsys, USA

Self-Optimization of Dense Wireless Sensor Networks based on Simulated Annealing
Alex Roschildt Pinto, Adriano Cansian, José Machado – universidade estadual paulista, Carlos Montez – universidade federal de santa catarina

Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy
Ahmed Rekik, route soukra, Florence Azais, Frederick Mailly, Pascal Nouet – univ. montpellier

11:30 – 12:30   SESSION 4: Product Quality and Software Testing
Session Chair: Adit D. Singh, Auburn University, USA

Investigating the Use of An On-Chip Sensor to Monitor NBTI Effect in SRAM
Arthur Ceratti, Thiago Copetti, Leticia Bolzani Poehls, Fabian Vargas –catholic university

Parametric DC and Noise Measurements for a Unified Production Line Characterization Framework Software Tool
Manuel Jimenez-Cedeno, William Morales, Lucianne Millan, , Rogelio Palomera – university of puerto rico at mayagüez, Frank Hou, Jose Rodriguez – texas instruments, inc.

Mutation Operators for Concurrent Programs in MPI
Rodolfo Silva, Simone Souza, Paulo Souza – Universidade de sao paulo

12:30 – 14:30  Lunch Break

14:30 – 15:30   SESSION 5: Automatic Test Generation
Session Chair: Vishwani Agrawal, Auburn University, USA

Automatic generation of an FPGA based embedded test system for printed circuit board testing
Jorge Hernan Meza Escobar, Jörg Sachsse, Steffen Ostendorff, Heinz-Dietrich Wuttke – ilmenau university of technology

Platform for Automated HW/SW Co-verification, Testing and Simulation of Microprocessors
Aleksandar Simevski, Rolf Kraemer – brandenburg university of technology, Milos Krstic – im technologiepark

About Robustness of Test Patterns Regarding Multiple Faults
Raimund Ubar, Sergei Kostin, Jaan Raik – tallinn University of technology

15:30 – 16:30  SPECIAL SESSION 2: Power- and Thermal-Aware Modeling and Design
Organizer: Jose Ayala, Complutense University of Madrid, Spain

Model-Based Design for Wireless Body Sensor Network Nodes
Ivan Beretta, David Atienza – embedded systems laboratory, Francisco Rincon – universidad complutense de madrid, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, Donatella Sciuto – Politecnico di milano

Fast and Scalable Temperature-driven Floorplan Design in 3D MPSoCs
Ignacio Arnaldo, , J. Ignacio Hidalgo, Jose L. Ayala, Jose L. Risco – complutense university madrid, Alessandro Vicenzi, Martino Ruggiero, David Atienza – epfl

Fast Worst-Case Peak Temperature Evaluation for Real-Time Applications on Multi-Core Systems
Lars Schor , Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele – ETH ZURICH

16:30 – 17:00   Coffee break

17:00 – 17:40   SESSION 6: Analog and Mixed Signal Circuits
Session Chair: Marcelo Lubaszewski, Federal University of Rio Grande do Sul (UFRGS), Brazil

Built-in Tunning of RFIC Passive Polyphase Filter by Process and Thermal Monitoring
Fayrouz Haddad, Wenceslas Rahajandraibe , Hassen Aziza, Karine Castellani-Coulie, Jean Michel Portal – Aix marseille UNIVERSITY

Multi-condition alternate test of analog, mixed-signal, and RF systems
Manuel Barragan, Gildas Leger, Jose Luis Huertas – UNIVERSIDAD DE SEVILLA

20:00 – 23:00   Gala Dinner

Friday, April 13th 2012

09:00 – 09:30   INVITED TALK: Pre-Computed Asynchronous Scan
Presenter: Vishwani Agrawal, Auburn University, USA      

09:30 – 10:10   SPECIAL SESSION 3: Thermal Aware Design and Test
Organizer: Marta Rencz, Technical University of Budapest, Hungary

Acquiring real-time heating of cells in standard cell designs
Andras Timar, Marta Rencz – BUDAPEST uNIVERSITY OF TECHNOLOGY AND ECONOMICS

Simulation Framework for Multilevel Power Estimation and Timing Analysis of Digital Systems Allowing the Consideration of Thermal Effects
Gergely Nagy, András Poppe – BUDAPEST uNIVERSITY OF TECHNOLOGY AND ECONOMICS

10:10 – 10:40   Coffee break

10:40 – 11:40  SESSION 7: Design and Synthesis for Testability
Session Chair: Fernanda Kastensmidt, Federal University of Rio Grande do Sul (UFRGS), Brazil

PSL Assertion Checkers Synthesis with ASM Based HLS tool ABELITE
Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov- tALLINN UNIVERSITY OF THECHNOLOGY, Samary Baranov – BAR ILAN UNIVERSITY

Retiming Scan Circuit to Eliminate Timing Penalty
Ozgur Sinanoglu – NEW YORK UNIVERSITY ABU DHABI, Vishwani Agrawal – AUBURN UNIVERSITY

IEEE STD 1149.1 Basics and Advance Topics,
FRANCISCO RUSSI – SYNOPSYS

11:40 – 12:40   SESSION 8: Harsh Environments: Radiation and EMI
Session Chair: Hervé Lévi, University of Bordeaux 1, France

Investigation of a CMOS Oscillator Concept for Particle Detection and Diagnosis
Karine Castellani-Coulie, Hassen Aziza,Gilles Micolau, Jean Michel Portal, Wenceslas Rahajandraibe – Aix-marseille university

SITARe: a SImulation Tool for Analysis and diagnosis of Radiation Effects
Gilles Micolau, Karine Castellani-Coulie, Hassen Aziza, Jean Michel Portal – Aix-marseille university

Impact of TID-induced Threshold Deviations in Analog Building-blocks of Operational Amplifiers
Guilherme Cardoso, Tiago Balen, Marcelo Lubaszewski – UFRGS, Rafael Vaz, Odair Gonçalvez – IEAv

12:40 – 14:00   Lunch

14:00 – 15:00   SESSION 9:  Dealing with Radiation Effects: SEUs and SETs   
Session Chair: Régis Leveugle, TIMA Laboratory, France

SET Susceptibility Estimation of Clock Tree Networks from Layout Extraction
Raul Chipana, Fernanda Kastensmidt, Ricardo Reis – ufrGs

Applying Adaptive Temporal Filtering for SET Mitigation based on the Propagation-Delay of Every Logical Path
Jose Eduardo Souza, Fernanda Kastensmidt  - UFRGS

SEU Fault-Injection in VHDL-Based Processors: A Case Study
Wassim Mansour, Raoul Velazco

15:00 – 16:00   SESSION 10: Software Fault Tolerance
Session Chair: Hans-Joachim Wunderlich, University of Stuttgart, Germany

Configurable Tool to Protect Processors against SEE by Software-based Detection Techniques
Eduardo Chielle, Raul Barth, Angelo Lapolli, Fernanda Kastensmidt – ufrgs

MoDiVHA: A Hierarchical Strategy for Distributed Test Assignment
Jefferson Koppe, Luis Bona, Elias Duarte Junior – federal university of Parana

Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems
Antoine Wecxsteen, Salma Bergaoui, Regis Leveugle –tIMA laboratory

16:00 – 16:30  Coffee Break

16:30 – 17:30   SESSION 11: Fault-Tolerant Architectures 
Session Chair: Vincent Pouget, University Bordeaux 1, France

Selective Hardening Methodology for Combinational Logic
Samuel Pagliarini, Gutemberg Junior, Lirida Naviner, Jean-François Naviner – telecom-paristech

Pattern-based Injections in Processors Implemented on SRAM-based FPGAs
Mohamed Ben Jrad, Regis Leveugle – tima laboratory

Non-intrusive fault tolerance in soft processors through circuit duplication
Felipe Silva, Frederico Ferlini, Eduardo Bezerra, Djones Lettnin – federal university of santa catarina

17:30 – 17:50   Closing Remarks

Saturday, April 14th 2012

Departure to Galapagos

Monday, April 16th 2012

19:00 – 20:00   PANEL SESSION:  Challenges of Advanced Nanotechnologies to Test Development