TTEP TutorialS

Design for Yield and Reliability

Yervant Zorian, Synopsys, USA
Email: Yervant.Zorian@synopsys.com

Abstract:

In addition to designing the functionality, today's SOC necessitates designing for yield and reliability. This requires embedding a special family of blocks to enhance the health and viability of the SOC. These blocks, also known as infrastructure IP, are meant to ensure silicon manufacturability and to achieve adequate levels of yield and reliability. Such Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such Infrastructure IP. Then, it concentrates on several examples of such embedded IPs for detection, analysis and correction.

Yervant Zorian, bio

Dr. Zorian is the Chief Architect at Synopsys, Mountain View, California. Formerly, he was Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice President and Chief Scientist of Virage Logic and chief Technologist at LogicVision. He received MS degree in Computer Engineering from University of Southern Califrornia, PhD in Electrical Engineering from McGill University, and MBA from Wharton School of Business, University of Pennsylvania.

He is currently the President of IEEE Test Technology Technical Council (TTTC), the Vice General Chair of Deisgn Automation Conference (DAC), the Editor-in-Chief Emeritus of Design & Test of Computers, the founder & chair of IEEE 1500 Standardization Working Group, and an Adjunct Professor at University of British Columbia. He served on the Board of Goverors of Computer Society and CEDA, and as the Vice President of IEEE Computer Society. He has been founder and chair of a number of workshops and symposia, including the IEEE Workshops on 3D-IC Testing, Design-for-Manufacturability & Yield, and East-West Deisgn & Test Symposium.

Dr. Zorian holds 29 US patents, authored 4 books, published over 300 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the Test Technology Technical Council (TTTC).

Statistical Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability

Adit D. Singh, Auburn University, USA
Email: adsingh@auburn.edu

Abstract:

As the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical adaptive screening methods are being developed. These attempt to improve test effectiveness and optimize test costs by Identifying ?suspect? parts that are then adaptively subject to more extensive testing, using additional tests that target the suspected failure mode. The basic idea is analogous to selective security screening approaches applied at airports. Such statistical methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. This tutorial presents test methodologies that span both these categories, and illustrates their effectiveness with results from a number of recently published experimental studies on production digital and analog circuits. Commercial tools offered by a number of new companies that have emerged in the "Adaptive Test" space will also be discussed.

Adit D. Singh, bio

Adit D. Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, where he directs the VLSI Design and Test Laboratory. His technical interests span all aspects of VLSI test and reliability. He has published over one hundred fifty research papers, served as a consultant for several major semiconductor companies, and holds international patents that have been licensed to industry. He has held leadership roles at international test conferences, including serving as General Chair of the 2000 IEEE VLSI Test Symposium, the 2003 IEEE Defect Based Test Workshop, and the 2004 IEEE Memory Test Workshop. He also serves on the editorial boards of IEEE Design and Test Magazine, and JETTA. Dr. Singh is a Fellow of IEEE, a Golden Core member of the IEEE Computer Society and is currently Chair of the IEEE Test Technology Technical Council.