Dr. Víctor Champac Vilela
Investigador Titular A

Correo: champac@inaoep.mx

Extensión: 1417

Información Curricular:

Líneas de Investigación:

Diseño de Circuitos Integrados
Testing

Proyectos:

Tesis:

Publicaciones Recientes:

Antonio Zenteno, Guillermo Espinosa, Víctor H. Champac, “Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops”, IEEE Transactions on very Large Scale Integration (VLSI) Systems, Vol. 15, No. 5, pp 572-577, May 2007.

Roberto Gómez, Víctor Champac, and Chuck Hawkins, “Stuck-Open Fault Aware in Advanced Technologies”, 8th IEEE Latin American Test Workshop, March 2007.

Daniel Iparraguirre, Víctor Champac, “Design of Digital Structures Tolerant to Local Intra-Die Process Variations”, IBERCHIP, March 2007.

Víctor Champac, Roberto Gómez, and Chuck Hawkins, “What Ever Happened to the Famous CMOS Stuck-Open Fault (aka - The Memory Fault)?”, Electronic Device Failure Analysis, Vol. 8., No. 3, August 2006.

F. Mendoza-Hernández, Mónico Linares, Víctor Champac, “Noise Tolerance Improvement in Dynamic CMOS Logic Circuits“, IEEE Proceedings of Circuits, Devices & Systems, Vol. 153, No. 6, December 2006.

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