inaoe.edu.mx
INAOE | Electronics | Nanoelectronics National Laboratory

The National Nanotechnology Lab (LNN)

Introduction

Mexico is falling behind in technological advances and in integrated circuit fabrication; this makes our country completely dependant on foreign production of high-technologies. The National Institute of Astrophysics, Optics and Electronics is aware of this severe limitation, and in the last few years has fought for the creation of national center for integrated circuit fabrication: The National Nanotechnology Lab (LNN). The LNN has two clean rooms for device and integrated circuit fabrication. The lab was started thanks to a donation of a device and integrated circuit fabrication line made to the INAOE by Motorola Inc. –a transnational company-.

Due to its large scale, the Project has been divided into two phases: The LNN Phase 1 or, MEMS Innovation Lab (LIMEMS) located at the INAOE facilities. The lab has an area of 800 m2 which is being converted into a class 10 cleanroom in fabrication equipment input ports and class 100 in all other areas. The lab received a grant of over 20 million pesos through SEDECO, with the support of the (SE) Department of Economy of the State of Puebla ($15M from the SE and $5M from SEDECO). With this grant, we have acquired fabrication equipment that complements the donation made by Motorola and consequently establishing lab facilities for development of MEMS prototypes and for studying the use of nanostructured materials in new devices and sensors.

Phase 2 of the LNN or LNN2, will result in a lab that will enable batch fabrication of semiconductor devices, Cls, sensors and MEMS. For this purpose, the construction of new class 10 building is planned, it will have 2000 m2 (process area). In addition to the already mentioned fabrications, the LNN2 will also carry out research and characterization of nanostructured materials, and study their applications in electronic and optoelectronic devices and sensors. In completing this phase, we have the support of the Department of Economy and the SEDECO, Puebla.

For Phase 2, the SE will finance ($12.5 million pesos) the construction of the building that will hold the clean room and SEDECO, Puebla, has already donated a two hectare plot of land for this project.


SEDECO will also aid in preparing the plot of land for this purpose, that is, service installment: pavement, telephone, etc. and supply everything else besides the actual construction of the class 10 clean room and the equipment for characterization. Equipment is needed for evaluating, testing and for the characterization and molding of this lab’s products, and for future developments in this type of applications.

General Objective


This project’s main objective is to create a world class lab for national technology development, focused on fabrication of: devices, integrated circuits and MEMS. The lab should be ahead of the industries’ needs through the incorporation of nanostructured materials to silicon technology. Highly trained human resources will be the lab’s contribution; they will have a modern and global vision of electronics. The LNN will act as a bridge between high level research and the industrial sector, which in turn, will lead to development in the national electronics’ industry and will benefit the university-industry-government environment, through a self sustainable and competitive project.

It will unify the efforts made by all institutions and national research centers that carry out research in electronics and related fields. This general objective can be achieved by combining basic and applied research within a broad range of research domains that range from the design of integrated circuits and fabrication technologies, to Microsystems and new fabrication techniques for printed circuits boards.

Specific Objectives

This project’s general objective can only be achieved through the completion of the following specific objectives:

Develop a national fabrication process for BiCMOS integrated circuits with a minimum dimension of 0.8 µm with low-k dielectrics incorporation and reduction of intrinsic parasitic capacitance.

Develop a national technology for fabrication of: Microelectromechanical Systems (MEMS) and Nanoelectromechanical Systems (NEMS).

Work with nanostructured materials, (obtain them, carry out characterization and apply them) making them compatible with silicon technology and for printed circuit board fabrication for personal computers functioning at clock rates superior to 10GHz.

Study, obtain and carry out characterization of innovative dielectrics with a high dielectric constant (k).

Study substrates with a high crystalline level in order to improve the mobility of charge carriers and raise device function.

Develop a fully-silicided (FUSI) fabrication process and study the function of silicides and their effects on high-k dielectrics.

Develop advanced devices, for example: (multigate devices -FinFET-) for conventional and high level substrates.

Develop silicon-based optoelectronic devices.

Develop high-frequency interconnections for chip to chip communications in printed circuits.

Device and material modeling

Carry out new design techniques that will optimize the use of devices and materials, making an emphasis on RF integrated circuits and optoelectronics.

CAD system development for modeling and characterization of: materials, processes and devices that result from this project.

Carry out collaboration projects with institutions and national research centers related to the field of electronics and other common areas.

Carry out projects in collaboration with the global electronics industry in order to be a part of this industry’s “Road Map”.

Double the INAOE Electronics Coordination’s research staff; in order to meet those objectives already stated and to abide by the Institutional Development Plan.

Offer prototype fabrication services and/or semiconductor device lots, MEMS and integrated circuits along with the process an materials that are developed here.
Raise the number of Electronics graduates (in the INAOE Electronics Postgraduate Program) to 30 doctorate graduates and 90 masters in science graduates per year. This will help create the necessary human resources that will make our country appealing to the high-tech Electronics’ Industry and will increase competitiveness.
Increase scientific production of the Electronics Coordination members, on average they must each produce two published articles (with arbitrage) a year; each researcher must have at least 4 yearly presentations in international conferences. (arbitrage in the field).
Will unify all efforts made by research centers and universities in Electronics development.

Serve as a driving force in developing a national electronics’ industry.

In order to make our country attractive to the high-technologies electronics industry, we will train necessary human resources (a critical amount) and generate jobs, this will contribute to elevate our competitiveness in this field that has a large impact and is prevalent.


Scientific Contribution

For over four decades the semiconductor industry has distinguished itself for its fast advancement in regard to products’ improvement. Main improvements in this field are: very high scale integration (number of components per chip), greater speed, lower power consumption and the design of products that are more compact and lightweight, with a larger memory capacity. One of the most frequent tendencies in this industry is often expressed as: “Moore’s Law”, which appeared in 1975 (for example, the number of chip components doubles every two years). This law’s most significant impact on society has been the reduction of costs per function. This has led those societies that own microelectronics’ technology, to increase their productivity and quality of life through the proliferation of computers, electronics’ communications and low cost consumer products.


The SIA, Semiconductor Industry Association Road Map, 2003 [1], sets the industrial production nodes for 2010, 2012 and 2016 at 45, 32 and 22 nm, respectively. As the Road Map also shows, this means that the future of the mentioned nodes presents considerable challenges. The era of the “Happy Climb” is over. The subsequent decrease in dimensions will no longer result in decrease of power and costs. Main challenges will be: to dispel power (due to current leaks in devices) and gain variability in fabrication processes.


The following steps are urgent: introduction of new materials (high and low constant dielectrics), new transistor architectures (multigate devices) that in combination with new advanced lithographic techniques, are necessary to continue the climb.
Long term actions must include replacing the “star” of the integrated circuit industry -silicon-, and introducing high mobility materials like Ge, in certain application areas or in compound semiconductors, like the II-V. The SIA considers the introduction of disruptive technologies such as carbon nanotubes or spintronics, in the distant future.

In agreement with the SIA’s main tendency, great scientific contributions can be achieved by maintaining a cheap substrate (beyond Moore’s law), that is competitive and abundant like silicon. Companies like Intel [2] work hard towards developing optical connections, operating in the silicon based THz range.

At the Electronics’ Coordination we have already achieved some progress in this respect and have reported silicon based detectors for wavelengths of up to 1.55 µm, operating at frequencies up to 45GHz [3]. In them, the base material is composed of Ge nanocrystals embedded in an amorphous Ge matrix; because this process is compatible with Si technology, we will continue working towards its integration with control circuits in the same substrate.

Regarding other materials that will be incorporated like the dielectrics, we have already proposed a-C:H for its k = 2.3, which was already proved in our lab [4]. We also suggest the use of peroskitas as high-k dielectrics, because they can grow epitaxially on Si and provide an interface that is uniform and free of defects on Si. In this way, current leaks are reduced, as well as low mobility; until now, these are among the greatest challenges that high-k materials have presented, they are suggested as gate dielectrics like: HfO2 or HfSiON [5].

The cases mentioned above are only a few examples of the contributions that will stem from this project. In sum, this will be a basic and applied research project on materials: nanostructured materials, fabrication technologies, new devices and their applications in integrated circuits, MEMS systems and the subsequent molding and design of new architectures and circuit/ systems topologies. These contributions will cover both scientific fields: basic and applied science.


Scientific Justification


The project’s scientific contributions are evident, it is completely scientifically justified because of this, it deals with the problems that the global electronics’ industry must solve for future generations of products.
Furthermore, it is important to mention that some specialists, like Gregory Timp have commented on the future of silicon technology [6], the author states: “It is possible that the CIs of the Si business may follow the same path the steel industry did by turning into a common use and low cost technology, while other technologies (plastics and aluminum) compete with steel in specific applications in which they offer lower costs or better performance. Even with these alternatives, steel continues to be the center of our mechanic culture and coexists with other technologies.” The same thing is expected from silicon technology, making it the cornerstone of alternate technologies.

For the reasons we mentioned, it is very important to us to justify what this project can achieve for our country. One of its main impacts will be regarding human resource training in Electronic science. The “Silicon Border” project is an important endeavor worth mentioning, this is an industrial park located in Mexicali B.C. and is meant for the installation of the semiconductor industry. It is expected that by 2010, over 10 “Wafer Fabs” (chip factories) will be installed. Each one of these factories will need at least 1,000 technicians in order to function, 30% of these must have a Masters or Doctorate Degree in Electronics. Through the realization of this project, this grave deficiency will be diminished in some manner, by way of experienced specialists in this type of highly specialized work. We also hope to influence in national Electronic Engineering studies’ programs, by providing new knowledge and experience in cutting edge electronics developed in our country.

The project also considers a technological transfer toward the existing global industry, if this should happen, in a matter of 10 years the LNN could become a self sustainable project. It will supply the developed product and transfer of its innovations and developments, in addition to creating enough income for sustaining newly created research positions and for updating research and fabrication equipment.


Connection to the Institutional Development Plan

The INAOE’s main mission as a Public Research Center is to “Contribute to knowledge creation, advancement and dissemination for the development of our country and humanity, through problem identification (scientific and technological) and also to pinpoint those problems concerning specialists’ training in the fields of: Astrophysics, Optics, Electronics and Computer Sciences, and other common areas”. Our vision focuses on: “Technological development and human resource training in the fields of Astrophysics, Optics, Electronics and Computer Sciences, as well as other common areas. We have a special commitment to national development through promotion of social values like solidarity, creativity and high competitiveness”.

This project shares the INAOE’s vision and mission. Furthermore, within the Institutional Development Plan we foresee infrastructure growth for materials and research. Our plan will include an increase in the Electronics’ Coordination research staff in 2007, with a total of 56 researchers; it is evident that our project will be in close connection to the Institutional Development Plan.

Conclusion


The project (in compliance with the Institution’s vision and mission) will also serve as a link between high technological level research and the industrial sector, this will impact the development of Mexican technology through the fabrication of integrated circuits, sensors and MEMS. Our country must increase its level of competitiveness in global electronics, in order to do so, we must promote and favor foreign investment, the only way to achieve this is by providing the industry with the highly trained human resources it needs. As a result, we must create cutting edge technology and stop being an “assembly plant” country. The LNN also aspires to promote combined actions between the industry, government and the academy in order to create a center for scientific-industrial development, that is competitive and self sustainable on an international level.


References

[1]. International Technology Roadmap for Semiconductors, published by the Semiconductor Industry Association, 2003.
[2] www.Intel.com/technology
[3] A. Torres Jácome, A. Murguía and R. Ramos, “A MSM Thin Film High Speed Photo-Detector Based on a-SiGe:H,F”, to be presented at the 2006 Joint International Meeting of the ECS, October 29 – November 3, 2006, Cancún México
[4] C. Zúñiga, A. Torres, A. Kosarev, “Carbon films deposited by low frequency plasma as Inter-metal dielectric”, J. Non Crystalline Solids, Vol. 329, pp. 175-179, 2003.
[5] For examples see, C.-T. Chan et al. “Characteristics and Physical Mechanisms of Positive Bias and temperatura Stress-Induced Drain Current Degradation in HfSiOn nMosfets”, IEEE Trans. On Electrón Devices Vol 53, pp. 1340-1436, 2006. Olivier Weber et al., “Fabrication and Mobility Characteristics of SiGe Surface Channel pMOSFETs with a HfO2/TiN Gate Snack”, IEEE Trans. On Electron Devices Vol 53, pp. 449-456, 2006
[6] Gregory Timp, “Nanotechnology”, Gregory Timp Editor, Springer-Berlag, 1999, Chapter 2, p 79.

 


 


Last Update:
01-12-2008 a las 14:48 por Anaís Infante

Address: Luis Enrique Erro # 1, Tonantzintla, Puebla, Mexico | Tel: (222) 247. 27.42 | Contact: mcampos@inaoep.mx | Fax: 247.27.42

 

This work is licensed under a Creative Commons License Attribution-Noncommercial-No Derivative Works 2.5 Mexico.

Creative Commons License