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March 11 - 14, 2007   |   Cuzco, Peru  

LATW2007 | Advance Program
 
Monday 12 march
8:30
Registration
9:00
Opening remarks
9:15
Embedded Tutorial
Low power digital circuits: are they harder to test?
Joan Figueras – Univ. Politécnica de Catalunya, Barcelona, Spain
10:15
Coffee break
Session 1:
Yield Optimization, Process Control and Measurements

Chair: Chuck Hawkins – University of New Mexico, USA
10:45
Non-square Meshes for Improved Yield in Nanotechnology Circuits
Costas A. Argyride, Dhiraj Pradhan, Univ. of Bristol., Dept. of Computer Science, UK.
S. Ramsundar – Dept. of Computer Science and Engineering, Institut of Technology, India
Ahmad Al-Yamanil – KFUPM, Dept. of Electrical Engineering, Saudi Arabia.
11:05
Statistical Analysis of Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies
Gustavo Neuberger, Fernanda Kastensmidt, Ricardo Reis – Univ. Federale do Rio Grande do Sul (UFRGS) , Instituto de Informatica, Brazil
Gilson Wirth, – UFRGS, Dept. of Electrical Engineering, Brazil,
Christian Pacha, Ralf Berderlow - Infineon Technologies, Germany
Session 2:
Design Verification/Validation

Chair: Cesar Dueñas (Freescale, Brazil)
11:25
Test Circuit for Functional Verification of Automatically Generated Cell Library
M. V. Gomes, C.A. Silva, S. Bavaresco, G. H. Sartori, L. Rosa Jr., R. P. Ribas – UFRGS, Institut de Informatica, Brazil
A. J. Reis – Nangate Inc., USA
11:40
Functional Verification of Communication Systems based on Modular Coverage and Data Mining,
Edgar Romero, Kleber Iguchi, Marius Strum, Wang Jiang Chau – Dept. of Electronic Systems, Polytechnic School, Univ. of Sao Paulo, Brazil
11:55
A Test Automation Framework for Mobile Phones
Luiz Kawakami, André Knabben – Motorola, Brazil Test Center
Douglas Rechia, Denise Bastos, Otavio Pereira, Ricardo P. Silva, Luiz Santos – Computer Science Department, Federal University of Santa Catarina, Brazil
12:15
Lunch
Session 3:
Fault Modelling, Analysis and Simulation

Chair: John P. Hayes – Univ. of Michigan, USA
14:00
What Ever Happened to the Famous CMOS Stuck-Open Fault (aka-The Memory Fault) ?
Victor Champac, Roberto Gomez – INAOE, Mexico
Chuck Hawkins – Univ. of New Mexico, USA
14:15

Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise
Michel Renovell, Florence Azaïs, Laurent Larguier - LIRMM, Univ. de Montpellier II/CNRS, France
14:35
A Model for the Analytical Definition of Multi-VDD, Multi-T Dynamic Tests in Nanometer Digital Circuits
Marcial Rodriguez-Irago, Juan J. Rodriguez-Andina – Univ. of Vigo, Electronic Technology Dept., Spain
J. Semiao – Univ. Algarve, Portugal.
Fabian Vargas – PUCRS, Electrical Engineering Dept., Brazil.
Isabel Teixeira, Joao Paulo Teixeira– INESC - ID Lisboa, Portugal
14:50
Defect and Fault Modelling of CMOS Active Pixel Sensors
Livier Lizarraga, Salvador Mir, Gilles Sicard – TIMA Labs., Grenoble, France
Andrei Draguilinescu – Politehnica Univ. of Bucarest, Rumanie
Session 4:
Analog and Mixed Signal Testing and Diagnosis

Chair: Florence Azaïs – LIRMM, Montpellier, France
15:10
Detecting Parametric Faults using TRAM
José Peralta, Gabriela Peretti, Eduardo Romero – Electronics and Control Research Group, Facultad Regional Villa María, Univ. Tecnólogica Nacional, Argentina.
Carlos Marques – Electronics and Instrumentation Development Group, Univ. de Córdoba, Argentina
15:25
Practical Implementation of Sinewave Generators for Mixed-Signal BIST
Manuel J. Barragán, Diego Vázquez, Adoración Rueda – IMSE-CNM-CSIC, Sevilla, Spain.
15:45
Bi-directional On-chip Jitter Measurement Circuit
Chaoming Zhang, Jacob Abraham – Computer Eng. Research Center, Univ. of Texas at Austin, USA
16:05
Coffee Break
16:20
Panel: "Software Testing vs. Hardware Testing: Synergy and Differences"Moderator: Magdy Abadir – Freescale, USA Panelists: Mateo Sonza-Reorda – Politécnico di Torino Jacob Abraham – Univ. of Texas, USA Diraj Pradhan – Univ. of Bristol, UK Yervant Zorian – Virage Logic, USA

 

Tuesday 13 march

9h00

Embedded Tutorial
System-on-Chip Test Infrastructure Design and Optimization
Zebo Peng – Linköping University

10h00

Coffee break

 

Session 5:
DFT, BIST and On-Line Testing

Chair: Christian Landrault – LIRMM, Montpellier, France

10:30

Reduced Switching Activity Tests for Broadcast Scan Based Designs
Joseph Howard, Santiago Remersaro, Sudhakar Reddy – Dept. of ECE, Univ. of Iowa, USA
Irith Pomeranz, School of ECE, Purdue Univ, USA.

10:50

AES vs. LFSR based test pattern generation: A Comparative study
Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre – LIRMM, Univ. Montpellier II, France

11:10

Fault Diagnosis in the BIST Environment Based on Bisection of Detected Faults
Raimund Ubar, Sergey Kostin, Jaan Raik - Tallin Univ. of Technology, Estonia

11:30

Software-Based Self-Test Strategies for Memory Caches of RISC Processor Cores Matthieu Tuna, Mounir Benabdenbi – Lab. LIP6, Dept. ASIM, Univ. Paris VI, France.

11:50

Digital Circuit Signal Integrity Enhancement by Monitoring Power Grid Activity
Jorge Semião – Univ. of Algarve/ EST, Portugal
Marcial Rodriguez-Irago, Marcelino Santos, Joao Paulo Teixeira, Isabel Teixeira – IST/INESC – ID, Portugal
Leonardo Piccoli, Fabian Vargas – PUCRS – Electrical Eng. Department, Brazil
J. J. Rodriguez Andina – Univ. of Vigo, Dept. Electronic Technologie – Spain

12:05

Lunch

 

Session 6:
System-on-Chip Test

Chair: Daniel Lupi – INTI, Buenos Aires, Argentina

14:00

Using static timing analysis and verification engines to generate native-mode tests for small delay defects
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham – Computer Eng. Research Center, Univ. of Texas at Austin, USA
Daniel Saab – Dept. of EECS, Case Western Reserve Univ., USA

14:20

On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics
Leticia Maria Veiras Bolzani, Edgar E Sanchez, Matteo Sonza Reorda – Politecnico di Torino, Italy.

 

Session 7:
High Level Software Testing

Chair: Alain Brun – Univ. Paris-Sud, France

14:40

Using Data Warehouse in Fault Injection Experiments
Janusz Sosnowski, Przemyslaw Zygulski, Piotr Gawkowski - Institute of Computer Science, Warsaw Univ. of Technology, Poland

15:00

A Tool for Structural Testing of MPI Programs
Alexandre Hausen, Silvia Vergilio – Federal Univ. of Parana, Brazil
Simone R.S. Souza, Paulo S. L. Souza, Adenilso Simao – State Univ. of Sao Paulo, Brazil

15:20

Evaluating a Fault-Based Testing Approach for XML Schemas
Maria Claudia F. P. Emer, Mario Jino – State Univ. of Campinas (UNICAMP), Brazil
Igor Nazar, Silvia Vergilio – Federal Univ. of Parana (UFPR), Brazil

15:40

Coffee break

 

Session 8:
Single Event Transient (SET) Modelling and Simulation

Chair: Pascal Fouillat – IMS, Bordeaux,France

16:00

SET Fault Injection Methods in Analog Circuits: Case Study

  1. Ammari, Lorena Anghel, Régis Leveugle – TIMA Labs, France
  2. Cristiano Lazzari, Ricardo Reis – UFRGS, Brazil

16:20

Single Event Transient Injection on an Operational Amplifier: A Case Study
John M. Espinosa-Duran,Jaime Velasco – Medina, Univ. del Valle, Cali, Colombia
Gloria Huertas, José L. Huertas – IMSE-CNM, Sevilla, Spain
Raoul Velazco, TIMA Labs., France

16:40

Tools and Methodology Development for Pulsed Laser Fault Injection in SRAM-Based FPGAs
Vincent POUGET, Alexandre Douin, Dean Lewis, Pascal Fouillat – IMS, Bordeaux, France.
Gilles Foucard, Paul Peronnard, V. Maingot, J. B. Ferron, L. Anghel, R. Leveugle, R. Velazco – TIMA Labs., Grenoble, France.

 

Session 9:
Single Event Upsets (SEU) Modelling and Simulation

Chair: Lorena Anghel – TIMA Labs., Grenoble, France

17:00

A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices,
Massimo Violante, Matteo Sonza Reorda, Luca Sterpone – Politecnico di Torino, Italy

  1. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella – Univ. di Padova, Italy
  2. Andreani, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli – Univ. di Roma, Italy

G. Gorini – Univ. di Milano Bicocca, Italy
C. Frost – Rutherford Appleton Laboratory, ISIS, UK

17:20

Error rate issued from a multiple upset injection method with realistic time distribution: a case study
Albert Ferrer – European Space Agency- ESTEC, Netherlands
Raoul Velazco – TIMA Labs., France
Robert Ecoffet – CNES (Centre Nat. D’Etudes Spatiales), Toulouse, France.

17:40

Sensitivity to SEUs Evaluation using Probabilistic Testability Analysis at RTL
José Fernandes, Marcelino Bicho Dos Santos, Arlindo Oliveira, Joao Paulo Teixeira – IST-TUL / INESC-ID, Portugal
Raoul Velazco, TIMA Labs, France

18:00

Fringe meeting(s)
19:30
Departure for social event

 

Wednesday 14 march

9h00

Embedded Tutorial 3 (T.B.D.)

 

Session 10:
Fault Tolerant Architectures and Techniques I

Chair: Salvador Mir (TIMA Labs, Grenoble, France)

10:00

Defect-Tolerant Nano-CMOS Logic Architecture: Exploiting the Inherent Redundancy of CMOS Logic
Abhijit Chatterjee, Maryam Ashouei, Adit Singh - Georgia Instititute of Technology, USA

10:20

A non-intrusive on-line control flow error detection technique for SoCs
Eduardo Rhod – UFRGS, Dept. de Eng. Elétrica, Brazil
Carlos Lisboa, Luigi Carro – UFRGS, Instituto de Informatica, Brazil
Massimo Violante, Matteo Sonza-Reorda – Politécnico di Torino, Dipt. de Automatica e Informatica, Italy

10:40

Coffee break

 

Session 11:
Fault Tolerant Architectures and Techniques II

Chair: Ricardo Reis (UFRGS, Brazil)

11:10

On the Use of Error Correcting Codes in Secured Circuits
Vincent Maingot, Regis Leveugle – TIMA Laboratory, France.

11:30

A Low Cost Checker for Matrix Multiplication
Carlos Lisboa, Marcelo Erigson, Luigi Carro – Insituto de Informatica, UFRGS, Brazil

11:50

Reducing TMR Resource Overhead in Hardened Carry-Select Adders
Eduardo Mesquita, Guilherme Corrêa, Matheus Braga, Helen Franck, Luciano Agostini, Jorge L. Guntzel – Univ. Federal de Pelotas (UFPel), Group of Architectures and Integrated Circuits, Dept. of Informatics, Brazil

12h05

Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs
Costas A Argyrides, Dhiraj Pradhan - Univ. of Bristol., Dept. of Computer Science, UK.
12h20
Concluding Remarks