Keynote Speech 1:

Nonlinear Computation and Sensory Processing in Emerging Technologies

Pedro Julián
Universidad Nacional del Sur – CONICET (Argentina)

This talk will present several architectures and chip realizations for nonlinear computation and sensory processing tasks. Piecewise linear computation is a particular case of nonlinear computation with an extremely efficient calculation procedure, where the accuracy can be defined with the size of an auxiliary memory. This approach has been successfully exploited in applications like pre-distortion of RF amplifiers, compensation of A/D converters and control of high-speed systems. When combined with parallel computation structures, as in the case of CMOS imagers with processing capabilities in the focal plane, complex computation can be performed by sharing resources. Examples will be given of silicon systems in nanometer-scale and 3D technologies.

 

Keynote Speech 2:

Mobile Computing: trends, challenges and opportunities

Maynard Falconer
Intel Labs (USA)

The pace of new computational products and expansion of their capabilities continues to accelerate and expand into new aspects of our lives.  What are the trends, what are they pointing to, and most importantly what are the opportunities and challenges the coming years will be presenting to us?  This talk will look at the cycle of disruptive innovation, future usages, form factor trends, and advances in power efficiency as both opportunities and challenges.

 

Keynote Speech 3:

Wafer Fab Foundries: Challenges and Opportunities

Alvaro Maury
SILTERRA (Malaysia)

A discussion on the wafer fab foundries challenges and opportunities will be presented, followed by a description of Silterra’s offerings; and the founder/CEO of RAMTRON and Symetrix, will discuss the advantages of embedded FeRAM, and the agreement with SilTerra to provide foundry services of devices that incorporate FeRAM.

 

Keynote Speech 4:

Plagiarizing nature for system analysis and design: why, when and how?

Mounir Boukadoum
Université du Québec à Montréal (Canada)

Systems composed of hundreds of processors and  multiple sensors integrated into single chips that autonomously satisfy their energy needs, self-organize in clusters, and intelligently adapt to their environment are becoming a reality. This example of system complexity brought forth by current technological advances has created many analysis and design problems that were either marginal or ignored in the past. Given the increasingly shorter design cycle and lifespan of the end products, the current formal tools for system design and analysis are often overwhelmed by these new problems, when not out of scope. This is not the case in nature where complex systems are common, and they have been dealt with successfully by an approach based on memory, experience and collaboration, as opposed to using logic and/or differential equations. 

In this talk, I will discuss the limitations of formal thinking when addressing today's complex system analysis and design problems, and how, by turning these problems into ones of classification and optimization, various nature-inspired techniques may be used to solve them, even in the presence of noise, non linear behavior, and fragmentary or unknown models. Applications in spectral identification and RF design will be presented as illustrative examples.

 

Keynote Speech 5:

Heterogenous fractal nano-structures in 3D:  revolutionary developments for the next generation integrated circuits

Maciej J. Ogorzalek
Jagiellonian University Krakow (Poland)

Recent developments in the area of integrated circuits include devices fabricated in heterogeneous materials/technologies, devices based on silicon nano-wires, graphene and carbon nano-tubes and carbon molecules fabricated in various technologies, hybrid structures connecting DNA and proteins to a nano-electronic substrate, heterogeneous components and sub-systems. 

The concepts of fractal geometries allow for the description and analysis of structures at nano-scale and also for development of new geometries and structures useful for construction of new devices and components such as hyper-capacitors, micro-batteries, new types of energy scavengers etc. for possible on-chip implementation.
Fabrication of new types of 3-dimensional systems-on-chip incorporating not only various types of signal processing functionalities but also energy generation and storage together with  power sources could offer revolutionary solution for construction of micro-systems independent of external power supplies.

This paper offers an in-depth overview of latest concepts and technologies developed in this fascinating area including hyper-capacitors, energy scavengers and micro-batteries showing an outlook to the possibility to integrate all these elements together in one 3D chip.

 

Keynote Speech 6:

Semiconductor Scaling and Reliability Implications for Advanced CMOS Technologies

Fernando Guarín
IBM Microelectronics Semiconductor Research (USA)

As we continue the relentless drive towards smaller semiconductor device feature sizes and higher levels of integration at the chip level for the 14nm node and beyond, it has become increasingly evident that a judicious review and a very complete understanding of the reliability mechanisms that contribute to the degradation of each of the technology elements will be crucial for the successful development of the most advanced leading edge technologies.
 
The increased device count, and process complexity, coupled with ever decreasing margins in voltage, geometry and the incorporation of new material systems such as; high and low k dielectrics, stress/strain layers. The path to maintaining the scaling cadence and new limiting factors will be discussed from the reliability perspective. A closer look will be given to Hot Carriers, Bias Temperature Instabilities and statistical variations (process and geometric).  This talk will present the reliability issues driven by the latest trends and state of the art in semiconductor fabrication as we continue to scale; it will also present the considerations necessary along with a practical approach to the qualification methodology required for leading edge CMOS technologies while providing a review of the specifications and implications of the above mentioned reliability mechanisms. The impact of reliability induced parameter degradation and the mitigation of these effects will be studied for practical circuits through the analysis of switching behavior and SRAM circuit applications.  The characterization, models and methodology will be put in the required perspective for the successful technology transfer of leading edge technologies to a manufacturing environment.