Program

	February 29	March 1	March 2
	8:00 and on Registration
8:30 – 9:00	Opening Ceremony
9:00 – 10:00	Keynote Speech 1	Keynote Speech 3	Keynote Speech 5
10:00 – 11:00	Keynote Speech 2	Keynote Speech 4	Keynote Speech 6
11:00 – 11:15	Coffee Break
11:15 – 12:35	Lecture Sessions LASCAS S1 LASCAS S2 LASCAS S3 IBERCHIP 1	IBERCHIP Poster Session	Lecture Sessions LASCAS S10 LASCAS S11 LASCAS S12 IBERCHIP 4
12:35 – 16:00	Lunch
16:00 – 17:20	Lecture Sessions LASCAS S4 LASCAS S5 LASCAS S6 IBERCHIP 2	Time reserved for Social Event	Lecture Sessions LASCAS S13 LASCAS S14 LASCAS S15 IBERCHIP 5
17:20 – 17:30	Coffee Break		Coffee Break
17:30 – 18:50	Lecture Sessions LASCAS S7 LASCAS S8 LASCAS S9 IBERCHIP 3		Lecture Sessions LASCAS S16 LASCAS S17 LASCAS S18
18:50 – 19:10			Closing
19:10 – 21:00

 

 

 

LASCAS S1: Analog Circuits I

S1-1 Cecilia Gimeno, Concepción Aldea, Santiago Celma and Francisco Aznar. A 1-V CMOS Front-End for High-Speed 1-mm SI-POF Links

S1-2 Andre Mariano, Olivier Mazouffre, Bernardo Leite, Yann Deval, Jean-Baptiste Begueret, Didier Belot, François Rivet and Thierry Taris. 65 GHz CMOS-SOI Low Power Consumption Voltage Controlled Oscillator

S1-3 Carlos Sanchez-Azqueta, Santiago Celma and Cecilia Gimeno. A Multi-Level Phase Detector in 90 nm CMOS

S1-4 Angélica Dos Anjos, Armando Ayala Pabón and Wilhelmus Van Noije. 2.45GHz Low Phase Noise LC VCO Design using Flip Chip on Low Cost CMOS Technology

LASCAS S2: Digital Circuits I

S2-1 Jorge Tonfat and Ricardo Reis. Low Power 3-2 and 4-2 Adder Compressors Implemented Using ASTRAN

S2-2 Fernanda Oliveira, Hugo Haas, José Gabriel Gomes and Antonio Petraglia. A CMOS Imaging System Featuring Focal-Plane Compression based on DPCM and VQ

S2-3 Duarte Oliveira, Thiago Curtinhas, Diego Bompean, Luiz Ferreira and Leonardo Romano. Synthesis of Synchronous Digital Systems Operating in Double-Edge of Clock

S2-4 Guanrong Chen, Optimal Homogeneous Networks with Best Possible Synchronizability

LASCAS S3: Computer Aided Design

S3-1 Gracieli Posser, Guilherme Flach, Gustavo Wilke and Ricardo Reis. Tradeoff Between Delay and Area in the Gate Sizing using Geometric Programming

S3-2 Jaime Vitola Oyaga, Adriana Carolina Sanabria Borbon, Cesar Pedraza Bonilla and Martha Johanna Sepulveda. Parallel Algorithm for Evolvable-Based Boolean Synthesis on GPUs

S3-3 Vinicius Livramento, Jose Luis Güntzel, Chrystian Guth and Marcelo O. Johann. Evaluating the Impact of Delay and Power Changes in Neighboring Gates in Discrete Gate Sizing

S3-4 Ryutaro Hayashi, Hidenori Ohta and Kunihiro Fujiyoshi. A Novel Representation for 3D-LSI Floorplan: Merged FT Squeeze

LASCAS S4: Signal Conversion

S4-1 Gustavo Della Colletta, Luis Henrique De Carvalho Ferreira and Tales Pimenta. A Low Power Successive Approximation A/D Converter based on PWM Technique

S4-2 Aldo Pena-Perez, Victor Rodolfo Gonzalez-Diaz and Franco Maloberti. Sigma-Delta Modulator with Op-Amp Gain Compensation for Nanometer CMOS Technologies

S4-3 Rafael Blumer, Cesar Prior, Paulo Aguirre and João Martins. High-Order Low-Distortion Switched-Current Cascade 2-2-2 ΣΔ Modulator

LASCAS S5: Digital Signal Processing I

S5-1 David Ernesto Troncoso Romero, Gordana Jovanovic Dolecek and Massimiliano Laddomada. Design of Multiplierless Linear-Phase Comb Corrector Filters for Multirate Applications

S5-2 Maurício F. Quélhas, Antonio Petraglia and Mariane R. Petraglia. Linear Programming for the Design of IIR Filters

S5-3 Angelo Luz, Eduardo Da Costa and Sidinei Ghissoni. Reducing Power Consumption in FFT Architectures by Using Heuristic-Based Algorithms for the Ordering of the Twiddle Factors

S5-4 Gregorio Bernabé, Ginés D. Guerrero and Juan Fernández. CUDA and OpenCL Implementations of 3D Fast Wavelet Transform

LASCAS S6: Sensor Technology

S6-1 Alexandre Simionovski and Gilson Wirth. A Bulk Built-in Current Sensor for SET Detection with Dynamic Memory Cell

S6-2 Joel Molina, Guillermo Espinosa, Alfonso Torres, Maria Teresa Sanz, Erick Guerrero, Berni Perez, Jose Fernandez, John Mckenna, Mazhar Hoque, Weize Chen, Tom Mcnelly, Richard De Souza and Patrice Parris. MIM-Based ISFET Sensors with CLOSED/OPEN Sense Plates for pH Detection. Comparison of their Sensitivity in Sub-Threshold and Strong-Inversion Modes.

S6-3 Daniel García-Romeo, Héctor Fuentes, Nicolás Medrano, Belén Calvo, Santiago Celma and Cristina Azcona. A NDIR-based CO2 Monitor System for Wireless Sensor Networks

S6-4 Francisco Castro-González, Arturo Sarmiento-Reyes and Francisco Zamudio-Saenz. Effects of Single-Electron Transistor Parameter Variations on Hybrid Circuits Design

LASCAS S7: Algorithm Applications

S7-1 Roman Held, Josef Goette, Marcel Jacomet, Christian Tanner, Marc Gonin and Martin Tanner. High-Speed Hardware Algorithm for Continuous Mode Time-of-Flight Mass Spectrometry

S7-2 Pilar Gomez-Gil, Omar López-Cruz and Ana Bertha Cruz-Martínez. Improving Neural-Based Classification of Databases with Overlapped Classes: the Case of Star/Galaxy Segregation

S7-3 Shadi Traboulsi, Nils Pohl, Josef Hausner, Attila Bilgic and Valerio Frascolla. Power Analysis and Optimization of the ZUC Stream Cipher for LTE-Advanced Mobile Terminals

S7-4 Martha Johanna Sepulveda, Guy Gogniat, Wang Jiang, Marius Strum, Ricardo Pires and Cesar Pedraza. Hierarchical NoC-based security for MP-SoC dynamic protection

LASCAS S8: High-Frequency Applications

S8-1 Alexandre De Oliveira Maniçoba, Héctor Dave Orrillo Ascama, Luiz Carlos Moreira, Sérgio Takeo Kofuji and Wilhelmus A. M. Van Noije. A CMOS UWB Pulse Beamforming Transmitter with Vivaldi Array Antenna for Vital Signals Monitoring Applications

S8-2 José Fontebasso Neto, Luiz Carlos Moreira and Wilhelmus Adrianus Maria Van Noije. Inductorless Very Small 4.6pJ/pulse 7th Derivative Pulse Generator for IR-UWB

S8-3 Adrián Rendón Nava, Alejandro Díaz Méndez and Luis Niño De Rivera Y Oyarzabal. Power Transmission on Intraocular Implanted Micro-systems: A review

S8-4 Fredy Segura-Quijano, Jorge Mario Garzón Rey, Antonio Garcia Rozo, Jesus Andres Palechor and Luis Felipe Ariza. Coil-on-chip: Design of integrated coils to inductive telemetry system

S8-5 Felipe Leal-Romo, Rogelio Moreyra-Gonzalez and Jose Rayas-Sanchez. HFSS Automated Driver based on Non-GUI Scripting for EM-based Design of High-Frequency Circuits

LASCAS S9: Processor Architectures

S9-1 Rogério Calazan and Nadia Nedjah. A Massively Parallel Reconfigurable Co-processor for Computationally Demanding Particle Swarm Optimization

S9-2 Claudia Patrica Renteria Mejia, Vladimir Trujillo and Jaime Velasco-Medina. Design of an 8192-bit RSA Cryptoprocessor based on Radix-4 Montgomery multiplier

S9-3 Luka Daoud, M. El-Sayed Ragab and Victor Goulart. Processor Allocation Algorithm based on Frame Combing with Memorization for 2D Mesh CMPs

S9-4 Henry Block and Carlos Silva. A digital hardware architecture for a three-input oneoutput zero-order ANFIS

LASCAS S10: Analog Circuits II

S10-1 Cristina Azcona, Belen Calvo, Santiago Celma and Nicolas Medrano. A Rail-to-Rail Differential Quasi-Digital Converter for Low-Power Applications

S10-2 Carlos Muñiz-Montero, Marco A. Ramírez-Salinas, Luis A. Villa, Heron Molina-Lozano, Victor H. Ponce-Ponce, David Arellano-Gutiérrez and Luis A. Sánchez-Gaspariano. A compact CMOS class-AB analog median filter

S10-3 Edson Santana, Raimundo C. Freire and Ana I. Cunha. A Compact Low-Power CMOS Analog FSR Model-Based CNN

LASCAS S11: Digital Signal Processing II

S11-1 Gerardo Molina Salgado and Gordana Jovanovic Dolecek. Non-recursive comb-decimation filter with an improved alias rejection

S11-2 Alfonso Chacon, Pedro Julian, Milutin Stanacevic, Shuo Li, Esteban Baradin and Leonardo Rivas. Low Power Switched Capacitor Implementation of Discrete Haar Wavelet Transform

S11-3 Eric Silva, Gordana Jovanovic and Fredric Harris. Cell Search in Long Term Evolution Systems: Primary and Secondary Synchronization

S11-4 Javier Vazquez Castillo, Alejandro Castillo Atoche and Johan Estrada. High-Speed Low-Power Parallel Random Number Generator for Wireless Channel Emulators

LASCAS S12: Modeling and Simulation

S12-1 Haulisson Jody Batista Da Costa, Francisco Assis Brito Filho and Pedro Ivo Araujo Do Nascimento. Memristor Behavioural Modeling and Simulations using Verilog-AMS

S12-2 Cristina Meinhardt and Ricardo Reis. Evaluation of process variability on current for nanotechnologies devices

S12-3 Carlos Hernández, Arturo Sarmiento and Héctor Vázquez. Existence of Multiple Operating Points in Memristive Circuits

S12-4 Guillermo Gallo, Gustavo Osorio and Gerard Olivar. Event-driven simulation of Filippov systems: The case of a nonlinear Wien bridge oscillator

LASCAS S13: Voltage References

S13-1 Dalton Colombo, Christian Fayomi, Gilson Wirth, Frederic Nabki and Sergio Bampi. Curvature Correction Method Based on Subthreshold Currents for Bandgap Voltage References

S13-2 Dalton Colombo, Felipe Werle, Gilson Wirth and Sergio Bampi. A CMOS 25.3 ppm/C Bandgap Voltage Reference using Self-Cascode Composite Transistor

S13-3 Miguel Rojas-Gonzalez, Joselyn Torres and Edgar Sanchez-Sinencio. Design of a Fully-Integrated Buck Voltage Regulator Using Standard CMOS Technology

S13-4 Miguel Rojas-Gonzalez, Joselyn Torres, Pavan Kumar and Edgar Sanchez-Sinencio. An Integrated Dual-Output Buck Converter Based on Sliding Mode Control

LASCAS S14: Signal Acquisition

S14-1 Janez Trontelj, Aleksander Sesek and Blaz Smid. Self-calibration of magnetic microsystem ASIC

S14-2 Diego Antolín, Alberto Bayo, Nicolás Medrano, Belén Calvo, Santiago Celma and Cristina Azcona. Analysis and Implementation of a Wireless Sensor Network with Remote Access through SMS

S14-3 Héctor Fuentes, Daniel García-Romeo, Nicolás Medrano, Belén Calvo, Santiago Celma, Cecilia Gimeno, María Teresa Sanz, Mario Moreno and Alfonso Torres. A SiGe Microbolometer Interface for Low-Power Microcontrolled Applications

S14-4 Erick Guerrero Rodriguez, Maria Teresa Sanz Pascual, Joel Molina Reyes, Nicolás Medrano Marqués and Belén Calvo López. A Digitally Programmable Calibration Circuit for Smart Sensors

LASCAS S15: Digital Circuits II

S15-1 Cezar Rodolfo Wedig Reinbrecht, Débora Matos, Marcio Kreuz, Luigi Carro and Altamiro Susin. MINoC: Providing Configurable High Throughput Interconnection for MPSoCs

S15-2 Andres Benavides Arevalo, Jose Aedo Cobo and Fredy Rivera. Multi-purpose System-on-Chip Platform for Rapid Prototyping

S15-3 Mohammad Hossein Hajkazemi and Amirali Baniasadi. HICPA: A Hybrid Low Power Adder for High-Performance Processors

S15-4 Duarte Oliveira, Noé Alles and Lester Faria. Synthesis by Direct Mapping of Extende Burst-Mode Asynchronous Controller Using RS Latch

LASCAS S16: Digital Circuits Applications

S16-1 Ernesto Cristopher Villegas Castillo, Mario Andrés Raffo Jara and Carlos Bernardino Silva Cárdenas. An Efficient Hardware Architecture of the H.264/AVC Half and Quarter-Pixel Motion Estimation for real-time High-Definition Video Streams

S16-2 Oscar González Díaz, Mónico Linares Aranda and Reydezel Torres Torres. The Influence of Interconnection Length on Expanded Non-Resonant Ring Oscillators

S16-3 Oualid Sanaa, Dominique Dallet and Eric Kerhervé. Design of a Mixed-Signal Cartesian Feedback Loop for a Low Power Zero-IF WCDMA Transmitter

LASCAS S17: Control Theory and Applications

S17-1 Blanca S. Leon, Alma Y. Alanis, Edgar Sánchez, Fernando Ornelas and Eduardo Ruiz-Velazquez. Neural Inverse Optimal Control Applied to Type 1 Diabetes Mellitus Patients

S17-2 Riemann Ruiz Cruz, Edgar Sánchez and Alexander Loukianov. Neural Backstepping Control: Green Energy Applications

S17-3 Nicolás Toro García, Fredy Edimer Hoyos Velasco and Fabiola Angulo García. Rapid Control Prototyping of a Permanent Magnet DC Motor Using Non-linear Sliding Control ZAD and FPIC

LASCAS S18: FPGAs

S18-1 Janier Arias-Garcia, Carlos Humberto Llanos, Mauricio Ayala-Rincon and Ricardo Jacobi. A fast and low cost architecture developed in FPGAs for solving systems of linear equations

S18-2 Alysson Shirai, Ricardo Jasinski, Eduardo Peters and Volnei Pedroni. Hardware-Efficient Location Discovery Based on Received Signal Strength Indication (RSSI)

S18-3 Jean Baptiste Ferron, Lorena Anghel and Regis Leveugle. Towards Low-cost Soft Error Mitigation in SRAM-based FPGAs: a Case Study on AT40K

S18-4 Daniel Muñoz Arboleda, Carlos Llanos Quintero, Leandro Dos Santos Coelho and Mauricio Ayala-Rincón. Accelerating the Artificial Bee Colony Algorithm by Hardware Parallel Implementations