IBERCHIP2018

PRIME-LA 2018

INAOE ITESO Innovative Design & Test Group

Monday, February 26th

Patrick Groeneveld

Distinguished Engineer, Cadence Design Systems, Inc, San Jose, CA


Abstract:
The extreme levels of integration technology pose ever larger challenges for design engineerings. Fortunately, IC design is one of the best automated synthesis methodologies in all of engineering. It crosses several levels of abstraction: from logic, to net list, to placed objects and eventually ending up in a mask pattern. Unlike other disciplines such as mechanical design, this flow is remarkably 'push-button'. The software ow for that consists of dozens of algorithmic steps that gradually transform the design, each time predicting and correcting the major quality objectives. Though individual algorithms are relevant, it is the intricate tuning of the interaction between the steps that makes or breaks a flow. This presentation will especially address the anatomy of a good flow, and what are good strategies for successful design closure. We will provide a broad overview and reason about the global trade-offs that make the flow robust and efficient even under the most complex design rules.


Short Bio:
Patrick Groeneveld was Chief Technologist at Magma Design Automation. He co-designed Magma's revolutionary RTL to GDS2 synthesis flow which is based on a pervasive use of a common data model. The core engine was a native sign-off STA tool that drives various logical and physical synthesis tools. After acquisition by Synopsys he worked on optimization in Design Compiler. Patrick was chair of the Design Automation Conference. He was also a full professor in EE at Eindhoven University. He holds a Ph.D. in EE from Delft University of Technology, the Netherlands. In his spare time, he enjoys flying, opera, his family and absorbing borderline useless information.

 

Themis Prodromakis

Prof. at University of Southampton


Abstract:
Progress in electronics performance has been achieved over the past 60 years via CMOS scaling, benefiting both mainstream design paradigms (analogue/digital). By virtue of operating in voltage (and continuous-time), analogue has been considered as inherently more powerful than the digital paradigm; however, over time scaling has favoured digital implementations over analogue in a rather disproportionate fashion. Yet nowadays, digital performance is also becoming increasingly difficult to pursue further due to fundamental physical scaling limitations. Simultaneously, reconfigurability has remained mainly in the domain of software engineering, relying for its physical implementation on dedicated memory blocks and progressively bottlenecked by power-hungry data transfers between physically separate memory and processing elements.
Recent advancements in nanotechnologies and smart materials have prompted the creation of a new class of devices which, compared to conventional CMOS transistors, are capable of achieving ‘more’ functionalities (e.g. multi-bit operation) for ‘less’ energy/space. The rich landscape of modern electronics design became even more diverse with the steady introduction of memristive technologies. The ability of memristors to act as electrically tuneable multi-level, non-volatile resistive loads, combined with their inherently scaling-friendly, low power and back-end integrable fabrication processes has rendered them a highly promising candidate for use in future electronics applications. These properties promote memristors as ideal candidates for achieving reconfigurability in a post-Moore and post-Von Neumann context, i.e. without relying on front-end integration density for performance and operating on the principle of separate, dedicated memory and processing elements. During this keynote, I will present how memristive technologies can be exploited in practical applications, with particular emphasis in the areas of memory and computation. I shall highlight the opportunities that this emerging technology brings for addressing the needs of modern massively parallel computing and identify the current challenges hindering their full potential.


Short Bio:
Prof Prodromakis is Professor of Nanotechnology and Head of the Electronic Materials and Devices Research Group in the Zepler Institute, University of Southampton, UK. He is recognized as a pioneer of metal-oxide Resistive Random-Access Memory technologies and is leading an interdisciplinary team comprising 10 researchers with expertise ranging from materials process development to electron devices and circuits and systems for embedded applications. He holds an EPSRC Fellowship, a Royal Society Industry Fellowship and is a Visiting Professor at the Department of Microelectronics and Nanoelectronics at Tsinghua University, CN and Honorary Fellow at Imperial College London. He is Fellow of the IET, Fellow of the Institute of Physics, Senior Member of the IEEE and serves as the Director of the Lloyds Register Foundation International Consortium for Nanotechnology (ICoN: www.lrf-icon.com). In 2015, Prof Prodromakis established ArC Instruments Ltd, a start-up that delivers high-performance testing infrastructure for automating characterisation of novel nanodevices.

 

Malgorzata Chrzanowska-Jeske

Prof. Electrical and Computer Engineering Department, Portland State University


Abstract:
For decades, VLSI chips where fabricated with CMOS technology, and planar MOSFETs as the basic units of the majority of designs. Through scaling the dimensions of a basic transistor were reduced from millimeters to micrometers and nanometers. Along the way advances in materials and processes brought the sizing of the transistors to the atomic distance limitations. The tutorial will start with a short discussion of the limitations of the most common planar silicon-based CMOS technologies. To fight various challenges like leakage, power and thermal issues, further developments became possible by extending the channels and gates of the transistors into 3D exploiting various 3D geometries such as for example FinFETS. To continue with this journey new technologies and new basic switching devices to be integrated into gigascale chips/systems are being developed. There are possible candidates like for example various 3D nanowire transistors, NWMOS. However, one of the most promising candidates for a building block of post silicon era integrated circuits is Carbon Nanotube Field Effect Transistor (CNFET) because of its excellent electronic and thermal properties. In the second part of the tutorial we try to give answers to two questions: “Can Carbon nanotube FETs deliver what they promise?” and “How to design reliable circuits with CNFETs in the presence of variations?” We conclude with presenting other applications in VLSI technology for CNTs and also grapheme. These applications include interconnect and heat distribution


Short Bio:
Malgorzata Chrzanowska-Jeske Malgorzata Chrzanowska-Jeske is Professor of Electrical and Computer Engineering and Director of the VLSI & Emerging Technology Design Automation Laboratory at Portland State University. From 2004 to 2010 she was Chair of the ECE department at PSU, which she joined in 1989. Previously, she has served on the faculty of the Technical University of Warsaw, and as a design automation specialist at the Research and Production Center of Semiconductor Devices in Warsaw. She holds M.S. degree in electronics engineering from Politechnika Warszawska (the Technical University of Warsaw) Warsaw, Poland, and the PhD degree in electrical engineering from Auburn University, Auburn, Alabama. Her research interests include CAD for VLSI ICs, MS-SOCs, 3D ICs, nanotechnology and nano/ bio systems, design for manufacturability and design issues in emerging and renewable technologies. She has presented tutorials, keynote and invited talks at various international conferences and events. She has published more than 150 technical papers and serves as a panelist and reviewer for the National Science Foundation (NSF), and as a reviewer for National Research Council Canada (NRC) and many international journals and conferences.
Her research has been supported by the NSF and industry. Dr. Chrzanowska-Jeske has served in various roles on the Technical, Steering, and Organizing Committees of many international conferences and workshops, and as Senior Editor, Associate Editor and Guest Editor of international journals. Currently, she serves as Associate Editor for Transactions on Circuits and Systems II. She served for two terms on Board of Governors of IEEE Circuits and Systems Society (CASS) where she was also Chair of the Distinguished Lecturer Program and Chair and a founding-member of Women in CAS. Currently, she serves as Vice President for Technical Activities for the IEEE Nanotechnology Council (NTC), and is chair elect of Nanoelectronics and Giga-scale Systems Technical Committee of the IEEE Circuits and Systems Society. She presented keynote, plenary and tutorial lectures at various international conferences. She received the Best Paper Award from Alabama Section of IEEE for the best IEEE Transaction paper in 1990 and IEEE Council on Electronic Design Automation 2008 Donald O. Pederson Best Paper Award in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems. She is a Life Senior Member of IEEE.

 

Tuesday, February 27th

Michel Maharbiz

Professor, Department of Electrical Engineering and Computer Science at the University of California, Berkeley


Abstract:
The emerging field of bioelectronic medicine seeks methods for deciphering and modulating electrophysiological activity in the body to attain therapeutic effects at target organs. Current approaches to interfacing with peripheral nerves and muscles rely heavily on wires, creating problems for chronic use, while emerging wireless approaches lack the size scalability necessary to interrogate small-diameter nerves. Furthermore, conventional electrode-based technologies lack the capability to record from nerves with high spatial resolution or to record independently from many discrete sites within a nerve bundle. Recently, we demonstrated neural dust, a wireless and scalable ultrasonic backscatter system for powering and communicating with implanted bioelectronics. We show that ultrasound is effective at delivering power to mm-scale devices in tissue; likewise, passive, battery-less communication using backscatter enables high-fidelity transmission of electromyogram (EMG) and electroneurogram (ENG) signals from anesthetized rats. These results highlight the potential for an ultrasound-based neural interface system for advancing future bioelectronics-based therapies.


Short Bio:
Michel M. Maharbiz is a Professor with the Department of Electrical Engineering and Computer Science at the University of California, Berkeley. His research focuses on the extreme miniaturization of technology focused on building synthetic interfaces to cells and organisms. He is known as one of the co-inventors of "neural dust", an ultrasonic interface for vanishingly small implants in the body. His group is also known for developing the world’s first remotely radio-controlled cyborg beetles. This was named one of the top ten emerging technologies of 2009 by MIT’s Technology Review (TR10) and was in Time Magazine’s Top 50 Inventions of 2009. Prof. Maharbiz received his B.S. from Cornell University and his Ph.D. from the University of California, Berkeley under nanotechnologist Professor Roger T. Howe (EECS) and synthetic biologist Professor Jay D. Keasling (ChemE); his thesis work led to the foundation of Microreactor Technologies, Inc. which was acquired in 2009 by Pall Corporation. He is a Senior Member of the IEEE (Engineering in Medicine and Biology Society) and a member of the Society for Neuroscience. Prof. Maharbiz is a recipient of the McKnight Foundation's Technological Innovations in Neuroscience Award (2017), a Chan-Zuckerberg (CZ) Biohub Investigator (2017), a Bakar Fellow (2014), recipient of a National Science Foundation CAREER Award (2009), a GE Scholar and an Intel IMAP Fellow. Michel’s long term goal is understanding developmental mechanisms as a way to engineer and fabricate machines.

 

Olivier Bonnaud

Professor Émérite, Université de Rennes 1 and Supelec-Rennes, France


Abstract:
The evolution of electronic circuits and systems is tightly linked to the phenomenal advances in microelectronics and nanotechnologies. The related incredible performance increase in computer and communications has led to the creation of new tools for higher education, mainly as online courses, which are accessible to everyone and everywhere. These tools include more and more contents, which facilitate understanding, such as animations, videos or simulations. Although these tools are very useful for the acquisition of knowledge, they are not well-suited to acquire know-how, an essential skill for engineers and technicians. The activities associated to the practice become unavoidable. Considering the extreme complexity of circuits and systems, modeling, designing, manufacturing or characterizing demand platforms increasingly expensive and difficult to implement. The pooling of these platforms is essential for guarantying up-to-date experimental setups. The French national microelectronics network allows this mutualization, the following of the technological evolutions and a financial support for developing innovative practical works. This paper deals with the developed strategy in France to share innovative practice and equipment in the field of electronic circuits and systems. The goal is to adapt the pedagogy for matching the needs of the future careers of our graduate students and engineers in the up-coming digital society. After a concise presentation of the context, several examples illustrate and discuss the practical activities developed in the frame of our French national network.


Short Bio:
Olivier Bonnaud (M95) ( SM’05) born in Marseilles (France) in 1950. Student at Ecole Normale Supérieure de Cachan from 1971 to 1975, he obtained the Master degree in 1973 at University of Paris-XI (France). He obtained his Ph.D in Microelectronics in 1978 at University of Lyon 1 and Docteur d’Etat es-science degree in 1984 in the same university.
He obtained the full professor position at University of Rennes 1 (France) in 1984 where he created the Microelectronics research lab that is today a department of IETR. He managed this laboratory during more than twenty two years. His research activities concerned mainly the polysilicon-based thin film technologies involved in integrated circuits and large area electronics, and sensors and actuators. He published and presented more than 300 papers in these topics. In 1984, he co-created the Common Center of Microelectronics of West (CCMO), a multi-institution center mainly devoted for higher education in microelectronics for the West part of France. He managed this center till 2010 when he was nominated by the Ministry of Higher Education as Executive Director of Public Interest Group CNFM (National Coordination for Education in Microelectronics and Nanotechnologies), a National structure that coordinates the French activities of higher education in microelectronics and nanotechnologies. He manages this GIP, since. He is since 2011 a Guest Professor at South-East University in Nanjing (China). He was awarded with the title of “1000 Talents” by the Chinese government in 2013, with a multiannual scientific grant to improve the microelectronics activities at South-East University. Strongly involved in education management as director of doctoral school from 2000 to 2012 in Rennes, and as Director successively of CCMO and of CNFM, he published or presented more than 200 papers in Journals and conferences on pedagogical purpose.

 

Wednesday, February, 28th

Andrei Vladimirescu

Delft University of Technology, Delft, The Netherlands, University of California, Berkeley, CA and Institut Supérieur d’Electronique de Paris, Paris, France


Abstract:
Advances in semiconductor and superconductor technology have sparked a new round of research in quantum computing in recent years. Quantum computers hold the promise to efficiently solve problems that are intractable by today’s electronic computers. In a quantum computer, standard logic bits ‘1’ and ‘0’ are replaced by quantum states |0〉 and |1〉 referred to as quantum bits (qubits). The challenge facing researchers is that these quantum states are preserved long enough to be detected only at sub-Kelvin temperatures.
Performing operations on qubits require an electronic interface for their control, which is implemented at room temperature today. This may work as proof of concept for the low number of qubits available at the present time; however, for the solution of practical problems the number of qubits will grow to tens of thousands making room-temperature electronics for control unworkable due to the wiring requirements, signal integrity and cost.
The solution is to build the control electronics to operate at 4 K or lower, which is the focus of our research. Standard CMOS is the technology of choice allowing both cryogenic operation (4 K down to below 1 K) and the integration of the billions of transistors required to operate a very large number of qubits.
The challenges and feasibility of building integrated circuits (IC) operating at 4 K and below will be described in this presentation.
As a first step, the operation of semiconductor devices at cryogenic temperatures needs to be verified by measuring and characterizing transistors. While transistor operation has been documented in a number of publications the physics governing the behavior of semiconductor devices at cryogenic temperature had to be understood and will be explained based on our results from two CMOS processes.
The next step once the physics is understood is to develop circuit simulation models, which accurately reproduce the characteristics measured at 4 K. The standard compact models available in SPICE simulators today guarantee accurate results only for the industrial temperature range of ICs from -70 to 125 oC. The behavior, additional physical effects and the upgrading of existing compact models will be detailed in the presentation.
The next challenge are the electrical design requirements of the interface circuits, which must process very small electrical signals with extreme accuracy and low noise while operating under a strict power budget (< 1 mW/qubit) imposed by the cooling limits of existing refrigeration technology. The SPICE models developed in this project have been used to design the control interface operating at cryogenic temperatures. Matching simulation with measurement for process characterization will be demonstrated and the design, simulation and implementation of a few critical circuit components, such as a CMOS low-noise amplifier for qubit sensing operating at 4 K, will be highlighted. The presented research proves that cryogenic CMOS is not only a viable technology but the preferred solution for the implementation of scalable electronic interfaces for quantum processors.


Short Bio:
Andrei Vladimirescu was a key contributor to the SPICE simulator at the University of California, Berkeley, releasing the SPICE2G6 commercial-grade SW in 1981. He pioneered electrical simulation on parallel computers with the CLASSIE simulator as part of his PhD and authored "The SPICE Book" published by J. Wiley and Sons. Currently he is Professor involved in research projects at the University of California at Berkeley, Technical University of Delft and the Institute of Electronics of Paris, ISEP, as well as consultant to industry. His research activities are in the areas of design, simulation and modeling of CMOS and beyond-CMOS circuits with applications for low voltage, low power and quantum computing. Andrei is an IEEE Life Fellow.

 

Gerhard Fettweis

Vodafone Chair Professor, cfaed (center for advancing electronics Dresden), TU Dresden


Abstract:
With every new generation of cellular we experience a 100x increase in peak data rate. However, what is often forgotten, the need for lowering the data rate is also prominent, as e.g. can be seen with the emergence of Narrow-Band IoT. Hence, multi-processor hardware platforms need to span more than 5 orders of bandwidth in data rate. In addition, with the advent of the Tactile Internet happening with 5G, demodulation latency requirements span more than 3 orders of magnitude. With the introduction of “network slicing” in 5G, any terminal can define its latency/rate requirement as needed to run the application. However, the hardware needs to follow suit, and it must be extremely energy efficient. The solution proposed here is to design extremely flexible MPSoC platforms which can adapt to the boundary conditions as needed. First IC design examples show the feasibility and potential.


Short Bio:
Gerhard P. Fettweis earned his Ph.D. under H. Meyr's supervision from RWTH Aachen in 1990. After one year at IBM Research in San Jose, CA, he moved to TCSI Inc., Berkeley, CA. Since 1994 he is Vodafone Chair Professor at TU Dresden, Germany, with 20 companies from Asia/Europe/US sponsoring his research on wireless transmission and chip design. He coordinates the 5G Lab Germany, and 2 German Science Foundation (DFG) centers at TU Dresden, namely cfaed and HAEC.
Gerhard is IEEE Fellow, member of the German Academy of Sciences (Leopoldina), the German Academy of Engineering (acatech), and received multiple IEEE recognitions as well has the VDE ring of honor. In Dresden his team has spun-out sixteen start-ups, and setup funded projects in volume of close to EUR 1/2 billion. He co-chairs the IEEE 5G Initiative, and has helped organizing IEEE conferences, most notably as TPC Chair of ICC 2009 and of TTM 2012, and as General Chair of VTC Spring 2013 and DATE 2014.

 





SUNDAY Y FEBRUARY 25

15:00 - 17:00 CASS Region 9 Chapter Meeting
17:00 - 19:00 LASCAS Steering Committee Meeting and LASCAS 2019 Organization Meeting
16:00 - 19:00 Registration
19:00 - 20:00 Welcome Cocktail

Preliminary Program


MONDAY FEBRUARY 26

Time Room: Violeta Room: Tulipán Room: Jacaranda
8:30 - 9:00 Opening Ceremony
9:00 - 10:00 Invited Speaker:
Patrick Groeneveld, Cadence, USA

Automated Design for 7nm Chips and Beyond:
a Fresh Perspective

Room: Violeta & Tulipán
Chair: Ricardo Reis
 
10:00 - 10:30
Authors
Poster Session P1, coffee break and exhibit
Chair: Luis Hernández

(6) Ali Far Class AB Amplifier With Noise Reduction, Speed Boost, Gain Enhancement, and Ultra Low Power
14) Minas Kousoulis, Constantine Coutras and George Antoniou Minimum multiplier-delay 4D digital filter
(156) Jorge Sánchez, Abisai Ramírez, Rodrigo Jaramillo and Ramón Parra An all-digital physical and MAC layer architectures for a reconfigurable Bluetooth transmitter
(69) Vinicius Martins, Jerson Guex, Luciana Shiroma Montali and Wang Chau The Functional Verification of a Satellite Transponder
(70) Gordana Jovanovic Dolecek and Ramon Flores Rodriguez Novel Two-Stage Comb Filter for Multiple-of-Three Decimation Factors
10:30 - 12:30

SESSION L1 - Multi-Core and 3D
Chair: Malgorzata Chrzanowska-Jeske

(72) Aniseh Dorostkar, Arghavan Asad, Mahmood
Fathy and Farah Mohammadi
Optimization-based Reconfigurable Approach for Low-Power 3D Chip-multiprocessors


(112) Luciano Lores Caimi, Vinicius Fochi, Eduardo Wachter and Fernando Gehm Moraes
Runtime Creation of Continuous Secure Zones in Many-Core Systems for Secure Applications

(75) Carlos Sanabria and Mónico Linares-Aranda
An analysis of On-Silicon-Vias Stack in RF-CMOS Processes

(98) Felipe Rosa, Luciano Ost and Ricardo Reis
gem5-FIM: A flexible and scalable multicore soft error assessment framework to early reliability design space explorations

(28) Shadi Harb and William Eisenstadt
Structural Parameters Effect on Signal Integrity of Inter-Tier Vias in 3D Stacking Technology

(151) Mouna Kotti, Mourad Fakhfakh and Esteban Tlelo-Cuautle
Effect of the Design Space Sampling on the Design Performances

SESSION L2 - Analog Circuits Chair: Guillermo Espinosa Flores-Verdad

30) Benjamin T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti and Mario R. Hueda
An 8-bit 3.2GS/s CMOS Time-Interleaved SAR ADC with Non-Buffered Input Demultiplexing

(87) Fernando M. Cardoso, Marcio C. Schneider and Edson P. Santana
CMOS Analog Multiplier with High Rejection of Power Supply Ripple


(120) Karolinne Brito, Robson de Lima, Volker Kible and Raimundo Freire
A 2.45 GHz CMOS Active Quasi-Circulator with a Built-in Rectifier

(115) Fredy Montalvo, María T. Sanz and Belén Calvo
High-Precision Self-Compensated Fully-Integrated CMOS LDO Regulator

(27) Jorge Costa Jr and Tales Pimenta
CMOS Analog Front-End IC for EEG Applications with High Powerline Interference Rejection

SESSION L3 - Design
Chair: Marco Antonio Gurrola Navarro

(86) Lucas Compassi Severo and Wilhelmus Van Noije
A 10.9-uW/pole 0.4-V Active-RC Complex BPF for Bluetooth Low Energy RF Receivers

(34) Cecilia Gimeno, Denis Flandre and David Bol
Low-Power Half-Rate Dual-Loop Clock-Recovery System in 28-nm FDSOI

(110) Javier Alejandro Martínez Nieto, Nicolás Medrano Marqués, María Teresa Sanz Pascual and Belén Calvo López
An Accurate Analysis Method for Complex IC Analog Neural Network-Based Systems Using High-Level Software Tools

(64) Oscar Danilo Montoya Giraldo, Alejandro Garces, Fedérico M Serra and Guillermo Magaldi
Apparent Power Control in Single-Phase Grids Using SCES Devices: An IDA-PBC Approach

(117) Yao-Ming Kuo, Luis Pablo Seva, Leandro Arana, Cristian Marchese and Leandro Tozzi
Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library

(179) Leonardo Bandeira Soares, Morgana Macedo, Claudio Machado Diniz, Eduardo Costa and Sergio Bampi
Exploring Power-Performance-Quality Tradeoff of Approximate Adders for Energy Efficient Sobel Filtering
12:30 - 14:00

LUNCH

LUNCH

LUNCH

14:00 - 15:00

Invited Speaker:
Themis Prodromakis, University of Southampton, UK

Memristive Technologies: a Viable Pathway for Beyond Moore Electronics

Room: Violeta & Tulipán
Chair: Arturo Sarmiento Reyes
 
15:10 - 16:40

SESSION L4 - EDA 1
Chair: Víctor Grimblatt

(129) Luciana Mendes Da Silva, Guilherme Bontorin and Ricardo Reis
Reducing the Amount of Transistors by Gate Merging

(181) Lucas de Paris and Ricardo Reis
An Automated Methodology to Fix
Electromigration Violations on a Customized Design Flow

(150) Marcio Monteiro, Ismael Seidel and José Luís A. Güntzel
On the Calculation Reuse in Hadamard-based SATD

(182) Elias de Almeida Ramos, Guilherme Bontorin and Ricardo Reis
A Nonlinear Placement for FPGAs. The Chaotic Place

(68) Gerardo Diaz-Arango, Hector Decos-Cholula, Luis Hernandez-Martinez,Francisco Castro-Gonzalez, Roberto Ruiz-Gomez and Hector Vazquez-Leal
Off-line Route Planner Using Resistive Grid Method for Vehicle Guidance in Real-Time Applications

SESSION L5 - Communications
Chair: Roberto Murphy

(114) Thiago Bubolz, Ruhan Conceição, Mateus Grellert, Bruno Zatt, Luciano Agostini and Guilherme Correa
Fast and Energy-Efficient HEVC Transrating based on Frame Partitioning Inheritance

(143) Laura Medina-Marín, Ramón Parra-Michel, Aldo Orozco-Lugo and Maurico Lara
Analysis of packet arrival model for 802.11 protocol under hidden terminals and asynchronous MPR detection

(74) Jose Eduardo Chiarelli Bueno Filho and Wang Jiang Chau
On TLM Traffic Accuracy: A Multifractal Perspective

(128) Bruno Oliveira, Rafael Reusch, Henrique Medina and Fernando Moraes
Evaluating the Cost to Cipher the NoC Communication

(154) Leonardo Orozco, Ramón Parra, Fernando Peña, Rodrigo Jaramillo and Eduardo Romero
A Resource Efficient Symbol Synchronizer Implementation for the IEEE 802.11 Protocol

SESSION I1 - Circuits 1
Chair: Cecilia Gimeno

(9) Cleiton M. Marques, Carlos A. S. N. S. Longo, Roberto B. de Almeida, Cristina Meinhardt and Paulo F. Butzen
Impacto de Falhas Stuck-Open e Stuck-On em Células de Memória 6T SRAM de 16nm

(20) Tiago Curtinhas, Duarte de Oliveira, Vitor Torres and Osamu Saotome
A Design Flow for Synthesis of XBM Direct Output Synchronous FSMs for Heterogeneous Systems

(24) Juan Ayala, Arturo Sarmiento, Teresa Sanz and Gerardo Diaz-Arango
Metodología para Evitar Múltiples Puntos de Operación en un Circuito Schmitt-Trigger

(18) Albano Borba, Matheus Ferreira Pontes, Vagner Rosa and Cristina Meinhardt
Comparação de Desempenho de Arquiteturas de Somadores de nbits em 32nm

(17) Christian Luis, Christian Enrique Cano Salazar and Carlos Silva
A High-Effient Architecture for Calculating the Determinant in the N-FINDR Algorithm on Hyperspectral Image Processing

16:40 - 17:10
Authors Poster Session P2, coffee break and exhibit Chair:    Luis Hernández
(16) Chia-Chun Tsai Embedded Bus Switches on 3D Data Bus for Critical Access Time Reduction
(17) Hua Fan High-resolution ADCs for Performance Enhancement in Biomedical Imaging Systems
(46) Dalton Martini Colombo, Thaironi Menezes de
Brito and Flavius Vinicius A. Coimbra
An approach a new 1 V Supply Resistorless Voltage Reference using Schottky Diode
(52) Francisco Tubiello, César Marcon, Thais Weber,
Letícia Poehls and Fabian Vargas
A Path Energy Control Technique for Energy Efficiency on Wireless Sensor Networks
(106) Akram Hadeed and Farah Mohammadi Energy Efficient Hybrid LLC in Future 3D CMP
17:10 - 18:40

Embedded Tutorial:
Malgorzata Chrzanowska-Jeske, Portland State University, USA

From Planar CMOS via FinFETs to CNT FETs

Room: Violeta & Tulipán
Chair: Maciej Ogorzale   

IBERCHIP 2018
SESSION I2 - Instrumentation
Chair: Tales Pimenta

(5) Hyeonggil Joo
Current Control of Soft-Starter with Estimation of Motor Parameters from Nameplate Data
13) Haris Chaudhry, Cristopher Villegas, Mario Raffo and Carlos Silva
Motion Vector Prediction and Search Range Calculation Architecture for HEVC Motion Estimation

26) Duarte de Oliveira, Lucas Santana, Vitor Torres, Orlando Verducci and Lester Faria
An Approach for Speed-Independent Extended Burst-Mode FSMs with Enhanced Robustness

(27) Rafael Puyol and Matias Miguez
A 100nA Cardiac Sensing Channel with Automatic Offset Correction



TUESDAY FEBRUARY 27



Time Room: Violeta Room: Tulipán Room: Jacaranda
9:00 - 10:00

Invited Speaker:
Michael Maharbiz, University Of California At Berkeley, USA

Recent Advances in Neural Dust: an Ultrasonic Platform for Interfacing to Nerves and Organs

Room: Violeta & Tulipán
Chair: Andrei Vladimirescu  
 
10:00 - 10:30
Authors
Poster Session P3, coffee break and exhibit
Chair: Luis Hernández

(31) Carlos Andres Lara-Nino, Miguel Morales-Sandoval and Arturo Diaz-Perez Small Lightweight Hash Functions in FPGA
(59) Shrief Rizkalla, Ralph Prestros and Christoph
Mecklenbräuker
A Simplified Reference Proximity Integrated Circuit Card for HF RFID
(78) Alejandro Garcia-Santiago, Josefina Castaneda-
Camacho, Jose F. Guerrero-Castellanos and Gerardo
Mino-Aguilar
Evaluation of AODV and DSDV Routing Protocols for a FANET: Further results towards robotic vehicle networks
(96) Satomi Ogawa and Takahide Sato A High-Accuracy Capacitance-to-Time Converter for Capacitive Sensors
(65) Eder Rodriguez, Juan Avalos and Juan Sanchez Error Coded Affine Projection-Like Algorithm with Evolving Order and Variable Resolution for Acoustic Echo Cancellatio
(140) Higor Delsoto, Duarte de Oliveira, Lucas Santana and Lester Faria A Design Flow of Asynchronous Burst-Mode Circuits without Fundamental-Mode Timing Assumption
10:30 - 12:30

SESSION L6 - Non-Linear Systems and Applications
Chair: Ma. Teresa Sanz Pascual

(104) Sundarapandian Vaidyanathan, Esteban Tlelo-Cuautle, Jesus Manuel Muñoz-Pacheco and Aceng Sambas
A New Four-Dimensional Chaotic System with Hidden
Attractor and its Circuit Design

(82) Arturo Sarmiento and Yojanes Rodríguez Velásquez
Maze-solving with a Memristive Grid of Charge-controlled Memristors

(56) Miguel Garcia-Bosque, Adrián Pérez-Resa, Carlos Sánchez-Azqueta and Santiago Celma
A New Randomness-Enhancement Method for Chaos-Based Cryptosystem

(55) Adrián Pérez-Resa, Miguel García-Bosque, Carlos Sánchez-Azqueta and Santiago Celma
Chaos-Based Stream Cipher for Gigabit Ethernet

(99) Marina Sparvoli and Mario Gazziro
Resistive Switching phenomenon in graphene oxide doped with copper devices

(163) Javier Ardila and Elkim Roa
Stochastic Resonance in Bang-Bang Phase Detector Gain and the Impact on CDR Locking

SESSION L7 - Amplifier Design
Chair: Andrei Vladimirescu

(183) Roman Fragasse, Brian Dupaix, Ramy Tantawy and Waleed Khalil
Sense Amplifier Offset Cancellation and Replica Timing Calibration for High-Speed SRAMs

(21) Angel Abusleme, Renzo Barraza and Sergey Kuleshov
A Baseline Restorer for Charge-Sensitive Amplifiers in a 500-nm CMOS process

(39) Yao-Ming Kuo, Agustín Grosso, Flavio Galimberti and Juan Tántera
Analog Front-End Design of Contactless RFID Smart Card ISO/IEC14443A Standard - Compliant

(38) Guillermo Royo, Carlos Sanchez-Azqueta, Concepción Aldea, Santiago Celma and Cecilia Gimeno
Highly-Linear Transimpedance Amplifier for Remote Antenna Units

(95) Juan Castagnola, Hugo García-Vázquez and Carlos Dualibe
Design and optimisation of a cascode low noise amplifier (LNA) using MOST scattering parameters and gm/ID ratio

PRIME-LA 2018 SESSION P1
Chair: Ignacio Zaldívar Huerta

(1) Joakim Nilsson, Johan Borg and Jonny Johansson
Chip-Coil Design for Wireless Power Transfer in Power Semiconductor Modules

(2) Ariel Oroz De Gaetano and Martin Di Federico
Light Controlled Oscillator for Image Sensing

(4) Tiago Curtinhas, Duarte de Oliveira and Osamu Saotome
Design of Extended Burst-Mode Asynchronous State Machines using Synchronous CAD Tools

(5) Tiago Curtinhas, Duarte de Oliveira and Osamu Saotome
VHDLASYN: A Tool for Synthesis of Asynchronous Systems from of VHDL Behavioral Specifications

(6) Felipe Rosa
Early Evaluation of Multicore Systems Soft Error Reliability Using Virtual Platforms

(7) Orlando Verducci, Duarte de Oliveira and Lester Faria
Synthesis of QDI AFSMs from XBM Specifications
12:30 - 14:00

LUNCH

LUNCH

LUNCH

14:00 - 15:30

Industry Panel:
High Tech Industry in Latin America – With a Little Help from My Friends
Víctor Grimblatt, Synopsys Chile
Horacio Visairo Cruz, INTEL, México
Guillermo Espinosa, INAOE, México
Raúl Camposano, Sage Design Automation, USA

Room: Violeta & Tulipán
Chair: Víctor Grimblatt  
 
15:30 - 16:30

Invited Speaker:
Olivier Bonnaud, Université de Rennes / Supelec, France
Strategy for Higher Education in Electronic Circuits and Systems in the Perspective of the Up-Coming Digital Society

Room: Violeta & Tulipán
Chair: José Ernesto Rayas Sánchez  
 
16:30 - 17:00
Authors
Poster Session P4, coffee break and exhibit
Chair: Luis Hernández

(15) Ali Far Sub-1 Volt Class AB Amplifier With Low Noise, Ultra Low Power, High-Speed, Using Winner-Take-All
(41) Gabriel Fre, Felipe Beltran Mejia, Tales Cleber Pimenta and Danilo Henrique Spadoti Low loss air channel modulator for ultra high frequency operation
(144) Duarte de Oliveira, Kledermon Garcia, Lucas Santana and Lester Faria FPGA Implementation of High-Performance Asynchronous Pipelines with Robust Control
(107) Roberto M. Passos Jr., José A. Apolinário Jr., Maike M. Muzitano, Lucas B. Nazareth, Gabriel B. B. Ribeiro and Antonio L. L. Ramos On real-time implementation of the BNLMS algorithm using the SHARC ADSP-21489
(83) Angelos Giakoumis, Christos Volos, Jesus Munoz-Pacheco, Ioannis Stouboulos and Ioannis Kyprianidis Text Encryption Device Based on a Chaotic Random Bit Generator
17:00 - 18:40

SESSION L8 - Power Consumption
Chair: Cláudio Diniz

(97) Sidartha Carvalho, Lucas M. F. Harada, Rafael Lima, Carolina Barbosa, Daniel Cunha and Abel Silva-Filho
Identifying Power Consumption Signatures in LTE Conformance Tests using Machine Learning

(123) Ali Shiri Sichani and Wilfrido Moreno
Mathematical Model for Glitch Power Consumption To Study its Security Implication on Power Analysis Attacks

(136) Murilo Perleberg, Jones Goebel, Mateus Melo, Vladimir Afonso, Luciano Agostini, Bruno Zatt and Marcelo Porto
ASIC Power-Estimation Accuracy Evaluation: A Case Study using Video-Coding Architectures

(13) Sabi Bandiri, Francisco Rizo, Tales Pimenta and Danilo Spadoti
Energy Consumption Improvement Based on Adaptive FEC Code in Elastic Optical Network

(40) Jose Luis Silva Perales, Daniel Garcia Garcia and Carlos Franco Tinoco
Impedance vs coupling noise analysis and tradeoff on power delivery filters based on package layout interconnections

SESSION L9 - High Frequency Circuits
Chair: Sergio Bampi

(63) Luis Alberto Rodríguez-Meneses, Celso Gutiérrez- Martínez, Jacobo Meza-Pérez, J. Alfredo Torres-Fórtiz and Roberto S. Murphy-Arteaga
Design and Construction of Dual-Mode Micro-Strip Resonator Filters for the 950-1,450 MHz Band: Application as IF Filters in Microwave Transceivers

(93) Sebastian Birke, Wei-Jhe Chen, Gaojian Wang, Dominik Auras, Chung-An Shen, Rainer Leupers and Gerd Ascheid
VLSI Implementation of Channel stimation for Millimeter Wave Beamforming Training

(164) Carlos Hernan Rodriguez Reyes, Jose Luis Naredo Villagran, Omar Longoria Gandara and Ramon Parra Michel
Modeling of Microstrip Interconnects with Cylindrical Sub-Conductors

(76) Jonathan Martínez, Agustín Santiago Medina, Carlos Alberto Bonilla, José Manuel Arce and José Martín Villegaz
Experimental Analysis of Microstrip Antennas Using Techniques to Improve the Bandwidth

(131) Florent Torres, Eric Kerhervé and Andreia Cathelin
90° Hybrid Coupler Design Technique for Wideband and Multimode mm-Wave operations featuring lateral ground planes virtual expansion in 28nm FD-SOI CMOS technology

SESSION I3 - Process
Chair: Alfonso Torres Jacome

(1) Mauricio Pacio, Cesia Guarneros, Laura Elvira Serrano-De La Rosa, Jose Alejandro Garcia, Avelino Cortés-Santiago and Hector Juárez
Electrical Properties of Metal/Porous Silicon/Silicon Structures Infiltrated with Metalloproteins

(2) Mario Moreno, José De Jesús Martínez, Pedro Rosales, Sandra Baéz, Oscar Velandia, Alfonso Torres, Netzahualcoyotl Carlos, Roberto Ambrosio, Miguel Dominguez, Luis Hernández and Aurelio Heredia
Temperature Optimization of the Wet Texturing Process of c-Si Wafers for Improve the Short Circuit Current Density of Solar Cells

(19) Joaquín Salvador Córdova and Alfonso Torres Jacome
Aluminum Nitride Elemental Characterization for Piezoelectric Applications

(22) Israel Emmanuel Zapata De Santiago, Carlos Roberto Ascencio Hurtado and Alfonso Torres Jacome
Síntesis y Caracterización de Películas Delgadas de SiGe:H Nanoestructurado y su Aplicación Como Material Termoeléctrico

(23) Andres Felipe Jaramillo Alvarado, Joaquin Salvador Cordoba, Emmanuel Torres Rios and Alfonso Torres Jacome
Metodología de Diseño para Resonadores IDT Basados en AIN

20:00 - 23:00
CONFERENCE BANQUET
Room: Restaurante Gaviotas


WEDNESDAY FEBRUARY 28



Time Room: Violeta Room: Tulipán Room: Jacaranda
9:00 - 9:40 Invited Speaker:
Andrei Vladimirescu, University Of California At Berkeley, USA

CMOS at Cryogenic Temperatures: Devices, Modeling and Circuits
Room: Violeta & Tulipán
Chair: Sergio Bampi
 
9:40 - 10:10

Coffee break and exhibit Exhibits room

Exhibits room
10:10 - 11:10

SESSION L10 - EDA 2
Chair: Fernando Moraes

(111) Alexandre Cardoso, Nadia Nedjah, Luiza Mourelle and Yuri Tavares
Co-design System for Template Matching using Dedicated
Co-processor and modified Elephant Herding Optimization


(135) Duarte de Oliveira, Tiago Curtinhas, Lucas Santana and Lester Faria
A Novel State Assignment Method for XBM AFSMs without the Essential Hazard Assumption

(26) Douglas Lohmann, Fabrizio Maziero, Elço João Dos Santos Jr and Djones Lettnin
Extending Universal Verification Methodology with Fault Injection Capabilities

SESSION L11 - Converters
Chair: Matías Miguez

(122) Francisco Veirano, Pablo Pérez-Nicoli, Pablo Castro-
Lisboa and Fernando Silveira

Gate Drive Losses Reduction in Switched-Capacitor DC-DC
Converters


(12) Filipe Ramos, Tales Pimenta and Luis Ferreira
Design of a Low-Cost High-Performance Digital PWM
Controller for DC-DC Converters


(157) Shrikant Singh and Debashis Mandal
Sense Resistor-Free Analog Power Sensor for Boost Converter with 14.1% Gain Error and 9.4% Offset Error

SESSION I4 - Circuits 2
Chair: Belén Calvo López

(3) Arturo Sarmiento and Arvi Naranjo-Calderon
A Symbolic Harmonic Memristor Model Applied to a Chaotic Circuit

(6) Douglas Borges, Roberto Almeida and Cristina Meinhardt
Comparação das Arquiteturas de Multiplicadores Baugh- Wooley e Radix-2 Booth na Tecnologia de 16nm

(7) Duarte de Oliveira, João Brandolin, Orlando Verducci, Vitor Torres and Osamu Saotome
An Approach for the Design of Asynchronous NUL Convention Logic (NCL) Circuits using FPGA
11:10 - 12:10

SESSION L12 - Reliability
Chair: Ricardo Reis

(153) Rafael Schvittz, Matheus Pontes, Cristina Meinhardt, Denis Franco, Lirida Naviner, Leomar Rosa Jr and Paulo F. Butzen
Reliability Evaluation of Circuits Designed in Multi- and Single-Stage Versions

(100) Guillermo Antúnez, Mariana Siniscalchi, Fernando Silveira and Conrado Rossi-Aicardi
Variability-aware Design Method for a Constant Inversion Level Bias Current Generator

(118) Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco Rangel-Patino, Miguel A. Davalos-Santana, Edgar A. Vega-Ochoa and Jose Ernesto Rayas-Sanchez
Jitter Tolerance Acceleration Using the Golden Section Optimization Technique

SESSION L13 - Sensors
Chair: Olivier Bonnaud

(155) Luighi Anthony Vitón-Zorrilla and Jinmi Gregory Lezama-Calvo
Low-power embedded readout and processing system for ISFET sensors as measurement devices

(126) Marcus Prochaska, Kris Rohrmann, Marvin Sandner, Phil Meier and Frank Freund
A readout concept for AC-driven xMR sensors in automotive wheel speed applications

(57) Jorge Pérez-Bailón, Alejandro Márquez Marzal, Belen Calvo, Nicolas Medrano and Maria Teresa Sanz-Pascual
A 1V-1.75µW Gm-C Low Pass Filter for Bio-sensing Applications

SESSION I5 - Circuits 3
Chair: Mario Moreno Moreno

(4) Héctor De Cos, Gerardo Diaz, Luis Hernandez and Arturo Sarmiento
Generación Automática de Árbol y Matriz de Transformación Topológica para Modificación de Sistemas de Referencia Dentro del Análisis MNA

(16) Duarte de Oliveira, Vitor Torres, Rafael Lima and Leonardo Romano
Synthesis of XBM Asynchronous FSMs by De–Synchronization from One-hot Synchronous FSMs

(21) Oscar Jair Cinco Izquierdo, Maria Teresa Sanz Pascual, Luis Hernández Martínez and Carlos Aristóteles De La Cruz Blas
Generación de Funciones No Lineales mediante Aproximación PWL

(25) Duarte de Oliveira, João Brandolin, Vitor Torres, Orlando Verducci and Osamu Saotome
An Architecture for Self-Timed Asynchronous Pipeline Circuits using FPGAs
12:30 - 14:00

LUNCH

LUNCH

LUNCH

14:00 - 15:00

Invited Speaker:
Gerhard Fettweis, Technische Universität Dresden, Germany

On Platform Design for 5G Signal Processing Implementation

Room: Violeta & Tulipán
Chair: Maciej Ogorzalek
15:00 - 15:30

Coffee break and exhibit

Exhibits room
15:30 - 16:50

SESSION L14 - Applications Chair: Carlos Silva Cárdenas

(101) Martin Causa, Franco La Paz, Santiago Radi, Juan P. Oliver, Leonardo Steinfeld and Julián Oreggioni
A 64-channel wireless EEG recording system for wearable applications


(10) Pedro Alejandro Duarte Riveros and Eduardo Costa Da Silva
High Sensitivity GMI Gradiometer with an Active Interference Compensation System

(121) Walter José Lancioni, Fortunato Carlos Dualibe, Pablo Petrashin, Luis Toledo and Carlos Vazquez
Continuous Time Full-Feedforward MASH 2-2 Architecture for Sigma-Delta Modulators

(24) Braulio Cancino and Angel Abusleme
A Novel Current-Based CCD Clock Driver

SESSION L15 - Signal Processing
Chair: Jacobus W. Swart

(176) Marco Antonio Gurrola Navarro
Frequency-Domain Interpolation for Simultaneous Periodic Nonuniform Samples

(174) Aminadabe Dos Santos Pires Soares, Wemerson Delcio Parreira, Everton Granemann Souza, Sérgio Jose Melo Almeida, Claudio Machado Diniz, Chiara Das Dores Do Nascimento and Matheus Fuhrmann Stigger
Energy-Based Voice Activity Detection Algorithm using Gaussian and Cauchy Kernels


(42) Ariel Oroz De Gaetano, Martin Di Federico and Ariel Arelovich
ALPR Character Segmentation Algorithm

(53) Lyda Vanessa Herrera Sepúlveda, Gordana Jovanovic Dolecek and Alfonso Fernández Vázquez
Mathieu Functions for DFT Filter Bank Spectrum Sensing
16:50 - 18:20

EDS Panel:
The importance of Electron Device Research for the Semiconductor Ecosystem in Latin America

Participants:
Jacobus W. Swart, IMEC / UNICAMP, Brazil
Arturo Escobosa, CINVESTAV, Mexico
Fernando Guarín, EDS President / Global Foundries, USA
Wilfrido A. Moreno, ISTEC / University of South Florida, US

Room: Violeta & Tulipán
Chair: Roberto Murphy
18:20 - 19:00

Closing Ceremony and 2019 Conferences Announcement