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The IEEE Latin-American Test Symposium (LATS, previously Latin-American Test Workshop - LATW) is a recognized forum for test and fault tolerance professionals and technologists from all over the world, in particular from Latin America, to present and discuss various aspects of system, board, and component testing and fault-tolerance with design, manufacturing and field considerations in mind. Presented papers are also published in the IEEE Xplore Digital Library. The best papers of the 16th LATS will be invited to re-submit to the IEEE Design and Test of Computers, IEEE Transactions on Computer-Aided Design, Journal of Electronic Testing: Theory and Applications - JETTA (Springer) and Journal of Low Power Electronics - JOLPE (American Scientific Publishers).

General Chairs

Victor Champac – INAOE, Mexico
champac@inaoep.mx

Yervant Zorian – SYNOPSYS, USA
yervant.zorian@synopsys.com


LATS2015 Topics

- Analog Mixed Signal Test
- Automatic Test Generation
- Built-In Self-Test
- Defect-Based Test
- Design and Synthesis for Testability
- Design for Electromagnetic Compatibility
- Design for Reliable Embedded Software
- Design Verification/Validation
- Economics of Test
- Fault Analysis and Diagnosis
- Fault Modeling and Simulation
- Fault-Tolerance in HW/SW

 

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Program Chairs

Leticia Bolzani Poehls – PUCRS, Brazil
leticia@poehls.com

Vishwani Agrawal – Auburn University, USA
vagrawal@eng.auburn.edu

 

 

- Fault-Tolerant Architectures
- Memory Test and Repair
- On-Line Testing
- Process Control and Measurements
- Radiation/EMI
- HW-SW Integrity Checking to Prevent
  Attacks
- Software Fault-Tolerance
- Software On-Line Testing
- System-on-Chip Test
- Hardware Trust & Security Approaches
- Yield Optimization

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