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SEMINARIOS

La coordinación de electrónica cuenta actualmente con 4 departamentos principales de investigación: Microelectrónica, Diseño de Circuitos Integrados, Sistemas de Comunicación e Instrumentación Electrónica. Estos a su vez, agrupan las distintas actividades de investigación y desarrollo que se realizan en el instituto. Con el fin de difundir las distintas actividades que se realizan en las cuatro áreas, se ha establecido un seminario semanal interno en el cual se exponen algunos de los temas que los investigadores así como sus alumnos (a nivel de maestría y doctorado), desarrollan actualmente.

La información que a continuación se presenta pretende proporcionar un breve panorama de lo anterior con vistas a generar un interés específico en el posible candidato a incorporarse al instituto. Finalmente, las líneas de investigación (por área y por investigador) que aquí se presentan son solo una pequeña parte proporcional de la oferta disponible dentro de la coordinación de electrónica del instituto por lo que se invita al interesado a contactarse con el investigador de su interés (directorio) con el fin de resolver dudas y definir una posible línea de investigación durante su posgrado una vez que haya sido aceptado.

 

Periodo Año:

   
2015-08-25
Area:
Investigador Invitado
Filiación Institucional Dra Clauduia Reyes Betanzo
Resumen: Ver resumen
   
Lugar-Hora Auditorio Docente - 12:08
   
2015-09-01
Area:
Investigador Invitado
Filiación Institucional Dr. Joel Molina Reyes
Resumen: Ver resumen
   
Lugar-Hora - 12:09
   
2015-09-08 Development of emergent non-volatile memories based on the memristive effect
Area:
Investigador Invitado M. en C. Rene Valderrama Bernardino
Filiación Institucional Dr Joel Molina Reyes
Resumen: Ver resumen n this talk, details of the development of emergent non-volatile memories based on the memristive effect are addressed. We show the main features of Resistance Random Access Memories (ReRAM) which are fabricated in INAOE using nanostructured materials. They have the potential for introduction into the next generation of advanced non-volatile memory devices because of their simple structure enabling deep scalability, low power consumption, fast switching speed and very-low thermal budget. On the other hand, this type of memory devices exhibits the recently discovered _memristive_ effect (_memory resistance_), in which the resistive state of the gate oxide can be switched between high and low-resistance states. The structure of these ReRAM memories is quite simple since we have used a Metal-Insulator-Metal configuration (like an integrated capacitor consisting of two metal electrodes and an insulator) in which the gate dielectric is deposited by Atomic Layer Deposition (ALD), thus enabling the engineering of the gate oxide material to the atomic level in order to enhance the performance of these memory devices. Our results show the ReRAM performance in terms of a high resistivity window (large IOFF/ION ratio), number of switching cycles, low power consumption, high capacitance density and also, some characteristics associated to the processing of these structures like dependence on the quality of the Insulator-Metal interface and the stoichiometry of the gate oxide. Most importantly, we highlight the potential of ReRAM for their vertical integration into a CMOS-based Back-End-Of-Line (BEOL) processing, thus promoting a 3D integration density.
   
Lugar-Hora Auditorio Docente - 12:09
   
2015-09-22 Applications of Integrated Chaotic Systems to Robotics and Image Encryption
Area:
Investigador Invitado Dr. Esteban Tlelo Cuautle
Filiación Institucional Dr Esteban Tlelo Cuautle
Resumen: Ver resumen The design of multi-scroll chaotic attractors by using standard CMOS integrated circuit technology and field programmable gate arrays (FPGAs) is presented in this talk. First, experimental results are provided for the integrated design of a chaotic oscillator generating 3- and 5-scrolls, fabricated with a 0.5um CMOS technology and its process, voltage and temperature (PVT) variation analysis is given. This oscillator is used to implement a random number generator that is applied to an autonomous robot. Second, an optimized chaotic oscillator is realized by using an FPGA to generate from 2- to 6-scrolls by applying two numerical methods. The FPGA implementation avoids the use of multipliers by realizing single constant multiplication blocks, and it is used to transmit an image in a master-slave secure communication system.
   
Lugar-Hora Auditorio Docente - 12:00
   
2015-09-29 A comparison on the predictive control schemes for a permanent magnet synchronous machine
Area:
Investigador Invitado
Filiación Institucional
Resumen: Ver resumen Permanent Magnet Synchronous Machines (PMSM?s) are commonly controlled by using vector control schemes, however, this vector control schemes presents either a slow dynamic performance or a high ripple in the controlled variables. To overcome these problems predictive control schemes have been proposed in the literature. In this presentation, the comparison of the Model Predictive Control (MPC) and the Predictive Torque Control (PTC) for a Permanent Magnet Synchronous Machine is presented. It is shown that the use of predictive control schemes enhance the control of the PMSM, furthermore, the use of cost function that allows the designer to include non-linearity?s and constraints is presented. Finally, the hardware description of the control schemes is presented, and simulations using Matlab/Simulink and Active/HDL are presented to evaluate the performance of the proposed control scheme under dynamic and steady state opertation.
   
Lugar-Hora Auditorio Docente - 12:07
   
2015-10-06
Area:
Investigador Invitado
Filiación Institucional Dr Mariano Aceves Mijares
Resumen: Ver resumen
   
Lugar-Hora Auditorio Docente - 12:10
   
2015-10-20 Modeling of the Carrier Transport Properties of Nanostructured Devices with Application to Advanced Logic Technology
Area:
Investigador Invitado
Filiación Institucional Dr Joel Molina Reyes
Resumen: Ver resumen In todays advanced logic technology, faster and more reliable CMOS devices are required, and in the pursuit of these characteristics, ballistic transport is a feature that is always desirable, since no scattering phenomena will affect the transistor, thus, making it faster and more reliable because there will be no damage in the structure. However, ballistic transport is hard to obtain due to several phenomena masking this effect: thermal fluctuations at/above room temperature, poor-quality interfaces at the metal/dielectric/semiconductor structure, and of course, their corresponding scattering events during carrier transport whether from source-todrain or substrate-to-gate directions. Recently, due to the nanometer scales in which new devices are fabricated, highly confined MOSFET structures could promote the splitting of quantized Landau levels at the valence and conduction bands of the gate oxide, which in turn could promote ballistic transport. In this work, MIS structures were fabricated (in which ultra-thin high-k materials are used as gate oxides), in order to measure the carrier transport properties of these nanostructured devices and correlate them with their conduction mechanisms.
Also, analyzing the density of the gate leakage current in these devices (via a traversal electric field), we tried to obtain experimental proof of the ballistic transport via an external magnetic field applied directly to the structures. By promoting Landau quantization in highly confined structures, we expect to enhance the performance and/or reliability of these devices since no scattering phenomena will be involved during carrier transport. In this sense, we have been able to obtain lower gate leakage current in the Direct Tunneling mechanism from a MIS structure due to a highly confined gate oxide (4 nm in thickness) in which quantization of states was promoted by the application of an external magnetic field. Also, MOS transistors were fabricated at INAOE and characterized in order to measure the Density of States (Dit). Then an external magnetic field B was applied to the transistor?s structure and, depending on the magnitude and the direction of B, some of the transistor?s performance parameters (such as mobility, and Vth) were enhanced. Finally, FinFETs were measured with an applied external magnetic field, in order to promote ballistic transport in the gate current. However, direct proof of ballistic transport could not be obtained at this stage because of the multiple current sources within a FinFET?s 3D dimensional structure; instead, an insensitive point of magnetic field was obtained. This will be further investigated giving the ability of an external magnetic field which, applied directly on a transistor structure, could promote quantization and thus, enhancement on the performance and/or reliability parameters of even smaller devices.
   
Lugar-Hora Auditorio Docente - 12:00
   
2015-11-03
Area:
Investigador Invitado
Filiación Institucional Dr Mario Moreno Moreno
Resumen: Ver resumen
   
Lugar-Hora Auditorio Docente - 12:11

 

Seminario de Electrónica

El objetivo del Seminario es exponer a los estudiantes de Maestría y Doctorado a todas las áreas de investigación que se cultivan en la Coordinación de Electrónica, enriqueciendo así sus conocimientos, además de ofrecer un foro de discusión y crítica en el que pueden presentar públicamente sus avances de tesis. Este Seminario se lleva a cabo los martes a las 12:00, y es obligatoria la asistencia de todos los estudiantes del Posgrado en Electrónica.

 

Se hace una atenta invitación para asistir al Seminario de Electrónica que se llevará a cabo el próximo jueves 12 de julio de 2018.


Hora: 12:00
Lugar: Auditorio Docente

Ponente: Dr. Carlos A. de la Cruz Blas, Universidad Pública de Navarra, España

Título: "Estrategias de diseño microelectrónico para loT en escenarios hostiles”

Resumen:

La presentación se basa en dar un vistazo general del diseño de circuitos integrados necesarios en ecosistemas IoT operando en entornos hostiles, principalmente entornos de alta carestía energética. Es decir, entornos donde el recambio de baterías es inviable por el número o emplazamiento de los nodos, y donde la necesaria energía ambiental es escasa e intermitente (común en muchas aplicaciones indoor y/o con alta densidad de nodos). Así, de forma breve se darán las bases del paradigma IoT, los tipos de comunicación necesarios, interfaces de acondicionamiento de la señal, sistemas de captación, almacenamiento y gestión ambiental de energía. Finalmente se dará algunos ejemplos de aplicaciones prácticas.

 

Nota: la asistencia de las y los estudiantes de electrónica es obligatoria.

 

Seminario de Electrónica y Diseño Avanzado

 

Éste es un evento anual con duración de 3 días organizado por la Coordinación de Electrónica, con el apoyo de los siguientes capítulos IEEE: Circuitos y Sistemas, Dispositivos Electrónicos, Instrumentación y Mediciones, Comunicaciones e Ingeniería en Medicina y Biología. El evento cuenta además con el apoyo de INTEL. El programa del Seminario se compone de conferencias impartidas por invitados consolidados en su área de trabajo, provenientes de instituciones reconocidas internacionalmente, así como por Conferencistas Distinguidos de las sociedades de IEEE mencionadas.

Seminario de Electrónica y Diseño Avanzado 2017 https://www-elec.inaoep.mx/seminario2017/

Seminario de Electrónica y Diseño Avanzado 2018 (próximamente) 

 

 


Última modificación :
10-07-2018 a las 14:23 por Laura Toxqui Olmos

Dirección: Luis Enrique Erro # 1, Tonantzintla, Puebla, México C.P. 72840 | Teléfono: (222) 247. 27.42 | Contacto: secelec@inaoep.mx

 

Esta obra está licenciada bajo una Licencia Creative Commons Atribución-No Comercial-Sin Obras Derivadas 2.5 México

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