About 180 years ago, ‘relay’ -- the first digital signal amplifier -- provided us with the long-distance telegraph through electric wires. This is the beginning of the information society and ‘electrical engineering’ era. About 115 years ago, ‘triode vacuum tube’ -- the first analog/digital signal amplifier -- brought us ‘electronics’ that can manipulate the electron movement, as we wish, for use for wireless-telecommunication and machine-control. About 75 years ago, the ‘transistor’ was invented as the first solid-state amplifier for the purpose of device-size reduction in order to realize high-frequency and low-power operation. This is the origin of the device miniaturization for micro/nanoelectronics. The 10 millionths-times device-size reduction in the past 115 years has created billions/trillions-times device-performance increase in the operation speed, energy consumption, weight, and cost, bringing us to super-intelligent society in near future. The tremendous performance increase by the progress of ‘micro/nanoelectronics’ -- originated by the ‘invention of the transistor’-- was a totally new concept and the 3rd technological leap (The 1st and the 2nd leaps were ‘electrical engineering’ and the ‘electronics’). It is obvious that today’s intelligent society does not exist without the invention of the transistor. The road to reach the invention of the ‘transistor’ was, however, a long and hard trail because of the lack of semiconductor physics, high-purity semiconductor materials, and charge-control knowledge at the semiconductor surface, in the period of the 1920’s to the 1940’s. In this talk, I will start with the story of the transistor invention. Then, I will explain the development of the transistor technologies from the past to the present. Finally, I will predict the limit of the device miniaturization and future direction of the nanoelectronics evolution after reaching its limit.

Drastic power consumption reduction will drive the design of technologies and architectures of future integrated circuits. They will request less energy greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high-volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-dimensional integration of hybrid, heterogeneous technologies at the device, functional and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co integrated Low Power and High-Performance Logic, Memory devices and Nanosystems to serve data computing and storage, functional diversification and communication. Thanks to the new technological opportunities, alternative neuromorphic and quantum-based computing, are showing up. The future of Nanoelectronics will face the major concerns of being Energy and Variability Efficient (E.V.E.).

In small enough semiconductor devices, the electron mean free path for collisions with impurities and lattice vibrations exceeds the device size. Such collisionless electron transport is called “ballistic” or “quasi-ballistic”. The electron mean free path in silicon at room temperature is on the order of 20 to 50 nm. This is much greater than the 5 nm minimum feature size of modern silicon CMOS with channel lengths on the order of 20 nm. Such transistors are used, for example, in the iPhone 12. The current-voltage characteristics of the quasi-ballistic Si CMOS look similar to those of much longer transistors. But the physics of the ballistic transport is very different, counter-intuitive, and has important qualitative consequences for the design of the advanced Si CMOS integrated circuits. Since electrons hit contacts more often in short-channel devices, the measured field-effect transistor mobility is determined by “the ballistic mobility” proportional to the device length. At high frequencies, the electron inertia starts playing an important or even a dominant role. The device impedance becomes strongly affected by electron inertia. The waves of the electron density (plasma waves) enable the Si CMOS response well into the terahertz (THz) range of frequencies. At high excitation levels, these waves are transformed into shock waves. The rectification and instabilities of the plasma waves enable a new generation of THz and sub-THz plasmonic devices. These devices could be implemented in Si, p-diamond, III-V, and III-N materials systems. The 300 GHz band 6G Wi-Fi, advanced homeland security, VLSI testing, and cancer detection are but examples of applications of this plasmonic technology, which is sensitive to the phase of the impinging THz radiation. New emerging plasmonic applications include a field-effect transistor THz spectrometer, a traveling wave THz detector, a THz frequency to digital converter, THz scanning cyber hardware security, and tunable “twisted plasmon” absorbers.

The memristor, a moniker for memory resistor, is the missing circuit element that I conceived and published in 1971, via an axiomatic approach. Unlike the transistor, it is a 2-terminal device which remembers its past, upon open, or short-circuiting, its terminals. Although I have included a functioning memristor built from off-the-shelf electronic components in my 1971 paper, as proof of principle, it had no commercial value and had languished in the dust bin of history for 37 years, until May 1 2008 when the title “THE MEMRISTOR 'Missing' circuit element found” graced the cover of Nature, where the world's first sub 10 nanometer memristor was built at the HP lab by a group of researchers led by Stanley Williams. By virtue of its ultra-low nanowatt power dissipation, ultrafast nanosecond speed, and sub-10 nanometer scalability, memristors has since become the workhorse for post-Moore computing tasks, such as internet of things (IOT), vector-dot product computations in deep learning, real-time in-memory computing, and above all, emulating high-level brain functions. This talk will reveal several memristive devices that have been built as far back as 1801 but were mis-identified by renown researchers, including 3 Nobel laureates, leading to numerous inexplicable enigmas, which I have since resolved. Finally, I will offer my future vision of memristor applications, including the indispensable role assumed by memristors in executing my Edge of Chaos criteria and solving the Turing instability which Alan Turing, the father of computing, had failed to resolve. Last but not least, you will be treated to some exciting videos with deep implications of creating life itself!

Desde el arranque del Laboratorio de Microelectrónica del INAOE en 1974, se dio también inicio al desarrollo, depósito y/o crecimiento de materiales con algún interés o aplicación en dispositivos semiconductores. En esta charla se hace un recuento de los materiales en los que se ha realizado alguna investigación dentro de este laboratorio, desde su inicio hasta nuestros días.

El laboratorio de micro electrónica inicia labores en 1974. Desde entonces ha desarrollado tecnologías de fabricación de dispositivos de silicio y circuitos integrados. Inició con la fabricación de dispositivos bipolares, incluyendo circuitos integrados de la lógica de inyección integrada. Posteriormente se desarrollaron dispositivos Metal Oxido Semiconductor (MOS) y se tuvo una tecnología MOS complementaria, es decir se fabricaban circuito integrados con transistores N y P MOS. Además de las tecnologías de circuitos integrados en el laboratorio se ha hecho investigación en una variedad muy amplia de dispositivos como sensores de presión, de luz, celdas solares, etc. Actualmente, el que suscribe está integrando un grupo de trabajo para desarrollar la electrofotónica. La electrofotónica está en la frontera de la ciencia y se puede definir como la unión de la electrónica integrada y la micro-fotónica integrada en silicio. En está plática se presenta una reseña de las diferentes etapas por las que ha pasado el laboratorio de microelectrónica, y la perspectiva para el futuro.

En esta plática se presentará la experiencia tenida en el desarrollo de un paquete tecnológico de fabricación de circuitos integrados digitales en el INAOE el cual incluye la tecnología de fabricación, el método de diseño y el método de pruebas de circuitos integrados. Se mostrarán diversos circuitos integrados que se han fabricado utilizando esta tecnología, a fin de que los interesados o relacionados con esta área multidisciplinaria, tengan un panorama de lo que en México, y en particular en el INAOE, se puede lograr con tecnología propia.

En esta plática se dará una breve descripción de la infraestructura con la que se cuenta actualmente en el laboratorio de microelectrónica del INAOE. Así mismo se dará una descripción de las capacidades que se tiene para desarrollar materiales, así como dispositivos semiconductores.

En esta plática se dará una breve descripción de la infraestructura con la que se cuenta en el laboratorio de microscopía electrónica del INAOE. Así como de las capacidades que se tiene para el análisis de materiales y dispositivos semiconductores.

La medición de circuitos en oblea requiere equipo especializado y en el laboratorio de Microelectrónica se cuenta con unidades fuente-medidor, fuentes de voltaje, electrómetros, un panel de conmutación, un analizador de parámetros semiconductores y un probador semiautomático de obleas. Se muestra el área de medición de circuitos integrados en oblea del Laboratorio de Microelectrónica del INAOE.

Gate dielectrics have been the most critical component in MOSFETs, as they determine the drain current, threshold voltage, reliability, and so on. Since the commonly used SiO2 has faced the limitation in thickness, dielectric films with higher dielectric constants were strongly required. As a result of many material/deposition works around the year 2000, hafnium-based oxides were selected and implemented in a 45-nm technology node. But gate dielectric researches are still going on to overcome the short-channel effects. The talk here will focus on La-based oxides for achieving a high-k direct contact with the Si structure.

En este workshop se tratarán temas sobre: ¿Qué son las herramientas EDA? su importancia, los niveles de aplicación en el Diseño de Circuitos Integrados, las herramientas con las que cuenta el Laboratorio de Diseño de CIs y se llevarán a cabo unos ejemplos didácticos con las Herramientas de Synopsys, Cadence y Siemens.

Se realiza una interpretación breve a las ecuaciones del modelo teórico del transistor MOSFET y posteriormente se utiliza un circuito integrado fabricado en el Laboratorio de microelectrónica para obtener las curvas de salida y de transferencia del dispositivo. Se emplea el analizador de parámetros semiconductores SCS-4200 de Keithley.

The need for radiation detectors with high efficiency and wide-area coverage is of high importance in applications such as nuclear medicine, industrial imagining, environmental radioactivity monitoring, spacecraft applications, and homeland security. For these applications, the detector material should be able to strongly interact with high-energy particles, must withstand operation at high electric fields with negligible leakage current, possess high resistivity, and be industrially scalable at low-cost production. In this talk, we demonstrate that low temperature materials and device technologies used for flexible displays and IoT applications can also be used to demonstrate other diverse applications including large-area radiation sensors, transducers, energy storage, etc. We discuss efforts to develop novel integration schemes, circuits, memory, sensors as well as novel contacts, dielectrics and semiconductors and demonstrate the carefully manipulation of these materials and devices to enable large-area, high-performance and reliable sensing systems for thermal neutrons, rays, X-rays, and ultraviolet radiation. We also demonstrate an integrated neutron/ray sensor fully fabricated at UT-Dallas that includes wireless communication to a mobile device.

The next generation of all-solid-state energy storage devices, such as supercapacitors and pseudocapacitors, requires a wide operating temperature range to work under demanding conditions. Thin film solid-state batteries stand out as desired components to produce on-chip energy storage, sometimes known as ‘power on a chip’. Multilayer structures have been tried for this purpose. The characteristics of both electrodes and the solid electrolyte require careful choice to meet this need. We propose a thin-film battery using zirconia stabilized with yttria as the electrode separator (50-100 nm in thickness) and transition metal/oxides — like ruthenium oxide and gold — as electrodes. We show promising results, given that the figures of merit (stored energy and energy density) compete with other cutting-edge thin film energy storage devices. Galvanostatic charge-discharge showed a typical energy density of 200 mWh/cm3 @170 °C. While optimistic about the possibility of producing a usable battery for low temperature applications, several technical problems remain to be solved. One of them is the operating temperature: in our prototype the peak performance is at 175°C. Electrical studies of the Ru/YSZ/Ru help us to better understand the nature of the ionic conduction processes during the transition from the super-to pseudocapacitive regime as a function of the temperature. The transition from a super-to a pseudocapacitive behavior occurs at the temperature where redox reactions initiate at electrodes interfaces. Also, the oxygen vacancies play a decisive role to improve the energy storage, therefore, increasing the ionic conductivity (movement of ions through vacancies) of the YSZ electrolyte is key. It is shown that controlling the concentration of vacancies (by thermal annealing or varying the yttrium concentration) can increase the energy density. Our results are relevant for application as in-chip energy storage deposited directly in integrated circuitry, especially in harsh operating conditions.

Para el diseño de circuitos integrados CMOS de RF es necesario medir, caracterizar y modelar MOSFETs en el régimen de corriente directa, pequeña y gran señal. Se revisarán algunos de los conceptos introductorios para conocer los requerimientos para los experimentos que permiten llevar a cabo estas tareas, dando énfasis a las mediciones eléctricas que se llevan a cabo utilizando analizadores de redes vectoriales.

Aggressively scaled transistor technologies with metal gate/high-k stacks encounter additional reliability challenges beside bias temperature instability (BTI) in PMOS and NMOS devices, time dependent dielectric breakdown and hot carrier degradation. Time-zero variability and variability induced by device aging is a growing concern which needs to be modeled using stochastic processes. The physical nature of the stochastic process remains under debate and to support model development efforts large statistical data sets are essential. In addition, self-heating during reliability testing can be observed in novel device structures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices and needs proper attention. Furthermore, to increase the confidence in the discrete device reliability models, device-to-circuit correlations need to be established. In this presentation we discuss how to obtain stochastic BTI data for discrete SRAM and logic device beyond 3, address device-to-circuit correlations using ring-oscillators and explore self-heating effects in FinFET and SOI devices.

Repasaremos la historia de docenas de logros antes y después de la invención del transistor, su impacto e importancia en este camino y en nuestras vidas. También revisaremos brevemente el diseño a nivel transistor de los bloques analógicos más importantes en un sistema serdes.

Esta es una oportunidad para reflexionar la presencia del transistor en los elementos cotidianos y cuestionar sobre las tendencias del diseño electrónico en el dominio analógico. Las estrategias de diseño en circuitos analógicos dependen de la filosofía, experiencia y visión de los ingenieros y científicos. La diferencia radica en la forma de encontrar soluciones a los problemas de diseño: i) tomamos ideas existentes y las adaptamos para los nuevos circuitos y ii) buscamos un esquema innovador con el riesgo de reducir la confiabilidad de los sistemas analógicos.

Se presentará cómo surgió este laboratorio, sus instalaciones, equipamiento, personal con el que cuenta y sus principales objetivos.

El Centro de Diseño MEMS del INAOE (CD-MEMS INAOE) es un laboratorio de investigación que ofrece servicios académicos y tecnológicos. Los servicios se fundamentan en las técnicas de Microelectrónica, micromaquinado de volumen y de superficie. Con el micromaquinado de volumen se desarrollan diversos proyectos de investigación, tales como microelectrodos de silicio, estructuras 3D en sustratos de alto índice, además se están estudiando superficies de alto índice en silicio {1 0 0} para aplicaciones ópticas y estudio de física de superficies con heteroestructuras. Con el micromaquinado de superficie se han desarrollado diversos mecanismos con polisilicio y se han fabricado sensores de presión capacitivos. Adicionalmente se ha estudiado una técnica de fabricación de microcomponentes con electrónica flexible, con el uso de sustratos delgados de poyimida se fabrican electrodos planos para estimulación eléctrica de cornea y sensores capacitivos para monitorear presión en modo implantable en el cuerpo humano. El CD-MEMS desarrolla actividades de divulgación de la ciencia y la tecnología.

The main goal of the iSensMEX project is to articulate, complement and strengthen research, technological development, and open innovation capabilities of Mexican public research centers articulated by the National Council for Science and Technology (CONACYT), that are focused on advanced multifunctional and semiconductor materials, semiconductor devices, integrated electronics, as well as systems and instruments The latter is enabled in this project through the manufacturing and integration of intelligent sensors and actuators for their application in areas of energy, health and safety. The project includes the development of a complete 0.8 um CMOS fabrication process at INAOE, 2D/3D stacking and packaging capabilities of integrated solutions at CIDESI, as well as the development of four complete intelligent sensor systems: (1) for detection of arsenic in drinking water, (2) for detection of E. Coli bacteria in foods and beverages, (3) for detection of Creatinine in blood of patients with kidney diseases, and (4) for detection of structural vibrations in public transportation using piezoelectric ceramics. The recent results of the iSensMEX project will be presented, alongside the discussion about the potential of this project, that articulates five public research centers (CIATEQ, CIDESI, CIMAV, COMIMSA, and INAOE) and more than 100 people working together to attain its seven specific goals, to enhance the technological development related to semiconductors technology in Mexico.

Recientemente un nuevo tipo de material ha despertado el interés de numerosos grupos de investigación alrededor del mundo. Estos son los llamados aislantes topológicos (TI, topological insulators), materiales cuyo interior se comporta como aislante mientras que presentan estados superficiales de conducción, que resultan de la suspensión de la periodicidad de la red cristalina. Dadas estas exóticas características, se supone que en un futuro no muy lejano este tipo de material sea la base de dispositivos novedosos, computación cuántica o espintrónica. Entre los principales materiales que presentan estas características destaca el teluro de bismuto (Bi2Te3), estudiado ampliamente por sus propiedades termoeléctricas. Se presentará el crecimiento de Bi2Te3 por medio de transporte físico de vapor, que es una alternativa a las técnicas tradicionales como MBE, o CVD. Se ha estudiado el crecimiento sobre silicio de orientaciones (100), (111), vidrio y zafiro. Las estructuras han sido caracterizadas por difracción de rayos X, microscopía electrónica de barrido y espectroscopía Raman entre otras. En todos los casos la orientación de los cristalitos ha sido mayoritariamente en la dirección (0001), en particular en el caso de depósito sobre zafiro es epitaxial, coincidiendo con la estructura cristalina del substrato. La naturaleza de aislante topológico ha sido demostrada por mediciones de ARPES.

Se presenta una introducción en la microscopia electrónica de barrido, principios de operación, historia, estado actual y algunas aplicaciones de la microscopía electrónica de barrido y microscopía de haz de iones focalizados, en el estudio de materiales y dispositivos semiconductores.

En esta plática se verá el desarrollo de la electrónica desde sus inicios hasta la invención del transistor y los circuitos integrados, principalmente analógicos, cual ha sido el progreso de los circuitos analógicos, que aplicaciones tienen y cuál es su futuro. Por otro lado, se da una perspectiva de cómo ha sido la historia de los institutos donde se enseña esta técnica de diseño en Puebla y cuáles han sido los logros de los diseñadores salidos de dichas instituciones.

[Era Pre-COVID] La falta de circuitos integrados que actualmente se vive ha sido causada por factores como la compra masiva de chips por parte de las empresas de telefonía celular, como Apple y Samsung, para dar entrada a la red 5G durante la era pre-COVID. Además, se dieron sanciones comerciales impuestas a gigantes de la telefonía como Huawei que resultaron en compras masivas de chips antes de que las sanciones entraran en vigor. Esto ya mantenía extremadamente ocupada a la industria de la manufactura de semiconductores.

[Era Post-COVID] Aunado a estos efectos pre-pandemia, la declaración de la Pandemia COVID-19 llevó a los gobiernos del mundo a tomar ciertas precauciones para prevenir contagios masivos en entornos concurridos que llevaron a un paro temporal de empresas gigantes de la manufactura de semiconductores como TSMC, Samsung, Intel, etc. De igual forma, la confinación de las personas en sus hogares llevó a un incremento en el consumo de electrónicos como computadoras, teléfonos inteligentes, consolas de videojuegos y el hardware adquirido por empresas de software, video y cómputo que vieron un incremento exponencial en sus ventas como Netflix, AWS, Amazon, Microsoft, entre otras.

In 1990s and early 2000s, PZT and SBT had been extensively investigated for ferroelectric random access memory (FRAM) using 1T-1C (or 2T-2C) architecture for high density stand-alone memory applications. Unfortunately, this technique faced a scaling limit due to thickness scaling, 3D integration and compatibility to sub 100nm CMOS technology. Since ferroelectricity of Hf based oxide has been reported in 2011, the renaissance of ferroelectric begins for realization of not only conventional FRAM for NOR and embedded memory and steep slope transistors but also memory transistor (1T) for next generation SCM (storage class memory) and 3D cross-point devices for neuromorphic devices.

In this presentation, ferroelectric properties of atomic layer deposited Hf0.5Zr0.5O2 (HZO) thin films will be reported for the development of future ferroelectric random access memory capacitors. A 10 nm thick HZO sample annealed at 400°C for 60 s in an N2 atmosphere after TiN top electrode deposition showed large switching polarization (~45 μC/cm2) and low ferroelectric saturation voltage (~1.5 V) from pulse-switching write/read measurement tests. Furthermore, we successfully scale down thickness of HZO down to 4nm which enables various applications in sub 3nm technology node. This low thermal budget ferroelectric capacitor technique is expected to be adopted at the stage of backend process and 3D integration for novel applications. In addition, J. Kim’s lab activities, particularly related to advanced ALDs and their characterization, will be also introduced.

The invention of the transistor in 1947, coupled along with advances in materials, device layout and process integration of semiconductor devices over the last seven decades has enabled the exponential growth of the necessary products and technological innovations that have transformed the world. Our society depends on semiconductors for most facets of everyday life. The near future will bring a level of instrumentation that grows daily with ever increasing amounts of data along with the intelligence and ability to communicate and automate many processes and industries in what is now known as the Internet of Things (IoT), an area that will be progressing at much higher speeds thanks to the incremental deployment of 5G. As a result of all these advances the world is already smaller and flatter. The reality of living in a globally integrated world is upon us and is presenting us with many opportunities and challenges. This increased information content gives us a unique path to alleviate and find solutions to the very serious problems that pose some of the most important challenges facing the world today. In this talk we will provide a brief historical perspective of the most relevant milestones in the development of semiconductor technology and will provide an overview of the economics and supply chain currently producing the chips that are widely employed throughout the world. We will describe the role and interactions of Pure Play Foundries, Integrated Device Manufacturers and Fabless companies. We will spend some time addressing the implications for our planet, from geopolitical to our ability to survive the impending climate and ecological crisis.

El entregar un microprocesador a los clientes de servidores requiere de un servicio integral que se extiende mas alla del diseño y fabricación del chip de silicio. Antes de que un cliente de servidores use por primera vez un microprocesador en sus plataformas de centro de datos, se deben realizar una cantidad de simulaciones electricas para encontrar la “zona de aterrizaje” (es decir, las condiciones donde el microprocesador va a tener su mayor desempeño) del sistema microprocesador-paquete-plataforma. En esta presentación se da un vistazo al Intel Guadalajara Design Center y al proceso que se sigue para verificar que las plataformas de centro de datos estén diseñadas para cumplir con los requerimientos del microprocesador.

Durante esta conversación mostraré la historia de éxito de Continental R&D en México desde que iniciamos operaciones en el año 2000, las capacidades que tenemos, nuestra aportación a la movilidad global y los retos que enfrentamos en el diseño de la movilidad del futuro.

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