Víctor Champac Vilela
Coordinación de Electrónica
Víctor Champac Vilela /
Selected Conference Publications
  1. Hector Villacorta, Victor Champac, SebastiaBota, Jaume Segura, “FinFET SRAM Hardening Through Design and Technology Parameters Considering Process Variations, Radiation Effects on Components and Systems (RADECS), 23-27 September, 2013.
  2. Hector Villacorta, Jose Garcia-Gervacio, Victor Champac, SebastiaBota, Jaime Martinez, Jaume Segura, “Bridge Defect Detection in Nanometer CMOS Circuits using Low VDD and Body Bias”, IEEE Latin American Test Workshop, April 2013.
  3. Francisco J. Galarza-Medina, Jose L. Garcia-Gervacio, Victor Champac, Alex Orailoglu, “Small-delay Defects Detection Under Process Variation Using Inter-Path Correlation”, IEEE VLSI Test Symposium, pp. 127-132, May 2012.
  4. Jesus Moreno, Victor Champac, Michel Renovell, Low Voltage Testing for Interconnect Opens under Process Variations, Latin American Test Workshop, pp. 1-6, April 2012.
  5. Jesus Moreno, Victor Champac, Michel Renovell, “A New Methodology for Realistic Open Defect Detection Probability Evaluation under Process Variations”, pp. 184-189, IEEE VLSI Test Symposium, May2011.
  6. C. Martins, J. Semiao, J. Vazquez, V. H. Champac, M. Santos, I. C. Teixeira, J.P. Teixeira, “Adaptive Error-Prediction Flip-flop for Performance Failure Prediction with Aging Sensors”, pp. 203-208,   IEEE VLSI Test Symposium, May2011.
  7. Jose L. Garcia-Gervacio and Victor Champac, “Computing the Detection of Small Delay Defects  Caused by Resistive Opens of Nanometer ICs”, IEEE European Test Symposium,  pp. 126-131, May 2010.
  8. J.C. Vazquez, V. Champac, A.M. Ziesemer Jr., R. Reis, I.C. Teixeira, M.B. Santos and J.P. Teixeira, “Low-sensitivity to Process Variations Aging Sensor for Automotive Safety-Critical Applications”, IEEE VLSI Test Symposium,  pp. 238-243, April 2010.
  9. J.C. Vazquez, V. Champac, A.M. Ziesemer Jr., R. Reis, I.C. Teixeira, M.B. Santos and J.P. Teixeira , “Programmable Aging Sensor for Automotive Safety-Critical Applications, IEEE Design Automation & Test in Europe (DATE),  March 2010.
  10. J.C. Vazquez, V. Champac, A.M. Ziesemer Jr., R. Reis, Jorge Semiao, I.C. Teixeira, M.B. Santos and J.P. Teixeira, “Predictive Error Detection by On-line Aging Monitoring”, IEEE International on-Line Test Symposium,  pp. 9-14, July 2010.
  11. Julio Vazquez, Victor Champac, Charles Hawkins, Jaume Segura, “Stuck-Open Fault Leakage and Testing in Nanometer Technologies”, IEEE VLSI Test Symposium, pp. 315-320, May 2009.
  12. Daniel Iparraguirre Cardenas, Victor Champac, “A Design Methodology for Designing Logic Paths Tolerant to Local Intra-Die Variations, International Symposium on Circuits and Systems (ISCAS), p. 596-599, Seattle, USA, May 2008.
  13. Nestor Hernández-Cruz, Victor Champac, “Testing Skew and Logic Faults in SoC Interconnects”, IEEE Computer Society Annual Symposium on VLSI, pp. 151-156, France, April 2008.
  14. Roberto Gomez, Victor Champac, “Fault Simulation of Interconnect Opens”, 9th IEEE Latin American Test Workshop, pp. 17-22, February 2008.
  15. Daniel Iparraguirre Cardenas, Victor Champac, “Design of Digital Structures Tolerant To Local Intra-Die Process Variations”, XIII Workshop Internacional de Iberchip , March, 2007.
  16. Victor Champac, Nestor Hernandez, Joan Figueras, “Signal Integrity Verification for Complex ICs”,  European Electromagnetic Conference (EMC2006), pp. 27-31, September2006.
  17. Roberto Gomez, Alejandro Girón, Victor Champac, “Test of Interconnection Opens Considering Coupling Signals”,  IEEE International Symposium on Defect and Fault Tolerance, pp. 247-255, October 2005.
  18. Victor Champac, Antonio Zenteno, Jose L. Garcia, “Testing of Resistive Opens in CMOS Latches and Flip-flops”, 10th European Test Symposium, pp. 34-40, May 22-25, 2005.
  19. Victor Avendaño, Victor Champac, Joan Figueras, “Signal Integrity Verification using High Speed Monitors”,  9th IEEE European Test Symposium, pp. 114-119,  May 23-26, 2004.
  20. F. Mendoza-Hernandez, M. Linares, V. Champac, “The Noise Immunity of Dynamic Digital Circuits with Technology Scaling”, International Symposium on Circuits and Systems (ISCAS), Canada,  May 23-26, 2004.
  21. F. Mendoza-Hernandez, M. Linares, V. Champac, “An Improved Technique to Increase Noise-Tolerance in Dynamic Digital Circuits”, International Symposium on Circuits and Systems (ISCAS), Canada,  Mayo 23-26, 2004.
  22. Antonio Zenteno, Victor Champac, Michel Renovell, Florence Azais, “Analysis and Attenuation Proposal on Ground Bounce”,  IEEE Asian Test Symposium, December 2004.
  23. Victor Avendaño, Victor Champac, Joan Figueras, “Signal Integrity Loss in Bus line due to Open Shielding Defects”, 8th IEEE European Test Workshop,  May25-28, 2003.
  24. F. Mendoza-Hernandez, Monico Linares, Victor Champac, “A New Technique for Noise-Tolerant Pipelined Dynamic Digital Circuits”, IEEE International Symposium on Circuits andSystems (ISCAS) , Vol. 4, pp. 185-188, May2002.
  25. Antonio Zenteno, Victor H. Champac, “Resistive Opens in a Class of CMOS Latches: Analysis and DFT”, 19th IEEE VLSI Test Symposium, pp.138-144, May2001.
  26. Victor H. Champac, Antonio Zenteno, "Detectability Conditions for Interconnection Open Defects", 18th IEEE VLSI Test Symposium, pp. 305-311, May2000.
  27. Casimiro Gomez, Alfonso Cadena, Victor H. Champac, "Switching Noise due to internal Gates: Delay Implications and Modeling", Third IEEE International  Caracas Conference on Devices, Circuits and Systems (ICCDCS), March2000.
  28. Victor H. Champac, José Castillejos, Joan Figueras, “IDDQ Testing of Opens in CMOS SRAMs”, pp. 106-111, IEEE VLSI Test Symposium, April 25-30 1998.
  29. Victor H. Champac, J. Figueras, A. Rubio, “On a Highly Observable Static and Dynamic Signature for CMOS Circuit Testing”, 2nd IEEE International On-Line Testing Workshop, Biarritz, France, July- 8-10 1996.