Víctor Champac Vilela
Coordinación de Electrónica
Víctor Champac Vilela /
Selected Journal Publications
  1. Jesus Moreno, Michel Renovell, Victor Champac "Effectiveness of Low Voltage Testing to Detect Interconnect Open Defects under Process Variations", IEEE Transactions on VLSI Systems, 2015.
  2. Hector Villacorta, Jose Garcia, Jaume Segura, Victor Champac, "Low VDD and Body Bias conditions for Testing Bridge Defects in Presence of Process Variations", MicrolectronicsJournal, Elsevier, Vol. 46, Issue 5, pp. 398-403, May 2015.
  3. Jose L. Garcia-Gervacio, Alejandro Nocua, Victor Champac, "Screening Small-Delay Defects using Inter-Path Correlation to Reduce Reliability Risk", Microelectronics Reliability, Elsevier, Vol. 55, Issue 6, pp. 1005-1011, May 2015.
  4. Victor Champac, Hector Villacorta, Nestor Hernandez, Joan Figueras, "Skew Violation Verification in Digital Interconnect Signals Based on Signal Addition", IEICE Electronics Express, Vol. 11, No. 15, 2014.
  5. J. C. Vazquez, V. Champac, J. Semião, I. C. Teixeira, M. B. Santos, J. P. Teixeira, “Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion”, Journal of Electronic Testing: Theory and Applications, Springer, Vol. 29, Issue 3, pp. 289-299, June 2013.
  6. Hector Villacorta , Victor Champac, Roberto Gomez, Chuck Hawkins, Jaume Segura,  "Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths", IEEE Design & Test of Computers, Vol. 30, Issue 6, pp. 70-79, December 2013
  7. Hector Villacorta, Victor Champac, SebastiaBota, Jaume Segura, “Resistive Bridge Defect Detection Enhancement under Parameter Variations Combining Low VDD and Body Bias in a Delay Based Test, Microelectronics Reliability, Elsevier, 2012.
  8. J. Pachito, C.V. Martins, B. Jacinto, J. Semiao, J.C. Vazquez, V. Champac, M.B. Santos, I.C. Teixeira, J.P. Teixeira, “Aging-aware Power or Frequency Tuning withPredictive Fault Detection”, Sept/Oct 2012.
  9. Victor Champac, Julio Vazquez, Salvador Barcelo, Roberto Gomez, Chuck Hawkins and Jaume Segura, “Testing of Stuck-Open Faults in Nanometer Technologies”, IEEE Design and Test of Computers,   2012.
  10. J.C. Vazquez, V. Champac, A.M. Ziesemer Jr., R. Reis, I.C. Teixeira, M.B. Santosand J.P. Teixeira “Delay Sensing for Long-Term Variations and Defects Monitoring in Safety-Critical Applications", Analog Integrated Circuits and Signal Processing, Springer, Volume 70, Number 2, pp. 249-263, 2012.
  11. Jose Luis Garcia-Gervacio, Victor Champac, “Computing the Detection Probability for Small Delay Defects of Nanometer ICs”, Journal of Electronic Testing: Theory and Applications, Springer, Volume 27, Issue 6, pp. 741-752, December 2011.
  12. Gerard F. Santillan-Quiñones, Victor Champac, Roberto S. Murphy, “Exploiting magnetic sensing capabilities of Short Split-Drain MAGFETs”, Solid State Electronics-Elsevier, Vol. 54, pp. 1239-1245, 2010.
  13. Victor Champac, Victor Avendaño,  JoanFigueras, “Built-in Sensor for Signal Integrity Faults in Digital Interconnect Signals”, IEEE Transactions on VLSI Systems, Volume 18, Issue 2, pages 256-269,  February 2010.
  14. Roberto Gomez, Alejandro Giron, Victor Champac, “A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines”, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Volume 24 ,  Issue 6, Pages: 529 – 538, December 2008.
  15. Antonio Zenteno, Guillermo Espinosa, Victor H. Champac,  “DFT Techniques for Testing Opens in Undetectable Branches in CMOS Static Latches and Flip-Flops“, IEEE Transactions on VLSI Systems, Volume 15, Issue 5, pp. 572 – 577, May 2007.
  16. F. Mendoza-Hernandez, Monico Linares, Victor Champac,  Noise-Tolerance Improvement in Dynamic CMOS Logic Circuits“, IEE Proceedings of Circuits, Devices & Systems,  Vol. 153, No. 6,  pp. 565-573, December 2006.
  17. Victor Champac, Roberto Gomez, and Chuck Hawkins , What Ever Happened to the Famous CMOS Stuck-Open Fault (aka - The Memory Fault)?, Electronic Device Failure Analysis, Vol. 8., No. 3, August 2006.
  18. Victor H. Champac, Victor Avendaño, ”Test of Data Retention Faults in CMOS SRAMs using Special DFT Circuitries”, IEE Proceedings-Circuits, Devices and Systems, Volume: 151, Issue: 2,  pp. 78-82,  April 2004.
  19. Antonio Zenteno, Victor H. Champac, Joan Figueras,  “Signal X-Y Zoning to Detect Inter-signal Delay Violations, IEE Electronics Letters,  Vol. 38 No. 14,  pp. 686-688,  July 2002.
  20. Antonio Zenteno, Victor H. Champac, Joan Figueras, “Detectability Conditions of Full Opens in the   Interconnections”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol 17, Issue 2, pp. 85-95, April 2001.
  21. Victor H. Champac, Victor Avendaño, Monico Linares,  "A Bit Line Sensing Strategy to Test Data Retention Faults in  CMOS SRAMs", IEE Electronics Letters,  Vol. 36, Issue  14, pp. 1182-1183,  July 2000.
  22. Victor H. Champac, José Castillejos, Joan Figueras, “IDDQ Testing of Opens in CMOS SRAMs”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol  15, No. 1/2, pp. 53-62, August-October 1999.
  23. Victor H. Champac, Joan  Figueras, "Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects", Journal of Custom-Chip Design, Simulation, and Testing ,  Vol. 5, No. 3, pp.273-284, 1997.
  24. V. H. Champac, J. A. Figueras,  "IDDQ Testing of Single Floating Gate Defects using a two-Pattern Vector",  IEE Electronics Letters,  pp. 1572-1574, Vol. 32 No. 17, 15 August 1996.
  25. V. H. Champac,  A. Rubio, J. Figueras, "Electrical Model of the Floating Gate Defect in CMOS ICs: Implications on IDDQ Testing",  IEEE Transactions on Computer-Aided Design  of Integrated Circuits and Systems, Vol. 13, No.3 , pp. 359-369, March 1994.
  26. J.A. Segura, V.H. Champac, R. Rodríguez, J. Figueras, J.A. Rubio, "Quiescent Current Analysis and Experimentation of Defective CMOS Circuits", Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 3, No. 4, pp. 51-62,  December1992. ISSN: 0923-8174, DOI: 10.1007/BF00135337.
  27. V. H. Champac, J. Figueras, J.A. Rubio, "Logic Testability of Defective Floating Gate CMOS Latches", IEE Electronics Letters, Vol. 28, No. 25, pp. 2305-2306, December1992. ISSN: 0013-5194, DOI: 10.1049/el:19921483.
  28. Antonio Rubio, J. Figueras, V. Champac, R. Rodríguez, J. Segura, "Iddq secondary components in CMOS logic circuits preceded by defective stages affected by analog type faults", IEE Electronics Letters,  vol. 27, no. 18, pp. 1656-1658, August, 1991. ISSN: 0013-5194, DOI: 10.1049/el:19911035.