Continuous advancements in semiconductor technologies have made  possible faster circuits with more integrated functionality. This has been achieved  with shrinking transistor geometries and increasing of the interconnect  density. At the same time process variations has become an important issue in nanometer technologies. They play an important role in the operation and test of  high performance integrated  circuits. In nanometer circuits, assuring  proper quality of interconnect signals has also become critical issue. These perturbations affect the noise level and the skew of the interconnect digital signals.  Design methodologies for robust digital design oriented to reduce the impact of process variations are needed. To bear the higher noise levels in high performance integrated circuits noise-tolerant  digital circuit techniques are needed.