Trends in nanometer technologies that have an increasing number of metal layers and higher complexity of the manufacturing process increase failure modes such as open vias and metal bridges. Bridges and opens  are important source of defects in advanced technologies. Actual integrated circuits contain millions of transistors which are interconnected by several layers of metal wiring. The “vias” are vertical plugs to connect the metal conductors between the layers. A modern microcontroller of around half a square centimeter in size contains well in excess of ten million VIAs [Infineon intros test chip to eliminate VIA defects]. A defective  via (e.g. a one with partially missing material)   has a higher current density, and is more prone to suffer electromigration and lead to a chip failure. Resistive vias have become an important yield detractor in modern technologies.

We make strong research on Test in Nanometer technologies.  A test vector generation methodology to improve the detectability of interconnection opens by applying proper logic levels at the coupled signals has been proposed. This methodology uses layout information and a commercial stuck-at ATPG. It is also important to analyze and quantify the reliability risk posed by undetected small delays due to resistive opens. Small delay defects (SDDs) are an issue in modern nanometer technologies. These defects are not properly covered by typical test methodologies (e.g stuck-at and transition test sets) and can escape the test. SDDs can cause reliability issues in circuits. Hence, it is quite important to develop new test strategies targeting SDDs. We work in a methodology to compute the Detection Probability (DP) of resistive open and bridge defects using a statistical timing framework that takes into account process variations. Measures can be taken for those circuits presenting non-acceptable DP in order to improve the test quality.  More recently, we  work in analyzing  the information on signals inter-path correlation to distinguish SDDs in the presence of process variations.