Scaling of semiconductor technologies has made it possible to integrate circuits with increasing functionality, speed, and interconnect density. However, at the same time, it has become a critical issue to assure proper quality of interconnect signals.  Noise appears as a consequence of the electric and magnetic field perturbations on internal electrical nodes. These perturbations affect the noise level and the timing  of the interconnect digital signals.
A current design challenge is to assure acceptable signal integrity levels in order to have the correct performance of the overall system. Test of the signal integrity (e.g. noise, timing) using on-chip monitors appears as a good alternative for present and future nanometer integrated circuits. On-chip testing for SI faults and timing violations in digital interconnect signals, using built-in high speed monitors have been proposed. Novel test methodologies have been proposed. On other side, the signal integrity in shielded transmission bus lines is also an important issue. These lines are grounded to the substrate by vias. If a resistive open occurs in this ground connection the impact on signal interconnects may produce signal integrity violations.