Kaushik Roy is the Edward G. Tiedemann, Jr., Distinguished Professor of Electrical and Computer Engineering at Purdue University and Director of the Center for Brain-Inspired Computing (C-BRIC). He received his PhD from University of Illinois at Urbana-Champaign in 1990 and joined the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked for three years on FPGA architecture development and low-power circuit design. His current research focuses on algorithms, circuits and architecture for energy-efficient cognitive computing, computing models and neuromorphic devices. Roy has so far supervised 99 PhD dissertations, and his students are well-placed in universities and industry. He is the co-author of “Low Power CMOS VLSI Design,” both the first and second editions, published by John Wiley & McGraw Hill. Roy has received a National Science Foundation Career Development Award, IBM Faculty Partnership Award, ATT/Lucent Foundation Award, Semiconductor Research Corporation Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award, IEEE Circuits and Systems Society Technical Achievement Award (Charles Desoer Award), Distinguished Alumnus Award from the Indian Institute of Technology, and the Semiconductor Research Corporation Aristotle Award in 2015. He also has served as a Department of Defense Vannevar Bush Faculty Fellow; Global Foundries Visiting Chair at National University of Singapore and Fulbright-Nehru Distinguished Chair.

Said Hamdioui (http://www.ce.ewi.tudelft.nl/hamdioui/) is currently Chair Professor on Dependable and Emerging Computer Technologies and Head of the Computer Engineering Laboratory (CE-Lab) of the Delft University of Technology, the Netherlands. He received the MSEE and PhD degrees (both with honors) from TUDelft. Prior to joining TUDelft as a professor, Hamdioui worked for Intel (Califorina, USA), Philips Semiconductors R&D (Crolles, France) and Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: Dependable CMOS nano-computing (including Reliability, Testability, Hardware Security) and emerging technologies and computing paradigms (including 3D stacked ICs, memristors for logic and storage, and in-memory-computing).
Hamdioui owns two patents, has published one book and contributed to other two, and had co-authored over 250 conference and journal papers. He has consulted for many semiconductor companies in the area of memory testing. Hamdioui is a Senior member of the IEEE,  was Associate Editor of many journals (IEEE TVLSI, JETTA, etc.) and sill serves on the editorial board of IEEE Design & Test, and ACM  Journal on Emerging Technologies in Computing Systems (JETC). Hamdioui is the recipient of many international/national awards. E.g., he  is the recipient Best Tech Idea Award of The Netherlands in 2021, the European Commission Components and Systems Innovation Award for most innovative H2020 project, the 2015 HiPEAC Technology Transfer Award,  European Design Automation Association Outstanding Dissertation Award 2003, etc. He received many Best Paper Awards and nominations at leading international conferences (e.g.,  DATE 2020 and 2021, ITC 2021, ETS 2021, IVSLSI 2016, HPCS 2016, ICCD 2015, etc.)

Franco Fummi received the Laurea degree in Electronic Engineering at Politecnico di Milano in 1990 and the Ph.D.in Electronic and Communication Engineering in 1994 at Politecnico di Milano.In 1993 he was Research Assistant at the department of Computer Science of the University of Victoria (B.C.).In 1996 he obtained the position of Assistant Professor in Computer Science at the Dipartimento di Elettronica e Informazione of Politecnico di Milano where he remained until October 1998.In July 1998 he obtained the position of Associate Professor in Computer Architecture at the Computer Science Department of Università di Verona.Since March 2001 he is Full Professor in Computer Architecture at the Computer Science Department of Università di Verona. He is leading the Cyber-physical and IoT Systems Design (CISD) group of the Università di Verona, currently composed of more than 20 people and working on hardware description languages and electronic design automation methodologies for modeling, verification, testing and optimization of cyber-physical systems.The main research directions exploited by Franco Fummi are:

• Embedded system verification (Static verification - Dynamic verification- Semi-formal verification - Hybrid and real-time systems – Smart systems integration);
• Networked embedded systems (System/Network co-simulation - System/Network co-design - QoS-enabled design - Sensor networks and M2M systems);
• Embedded systems design (TLM-RTL synthesis and abstraction - RTL-to-SW abstraction - TLM transactor generation - Device-driver generation - Embedded SW for multi/many core systems - Middleware-based design).
• Cyber-physical production systems modeling, design, simulation and testing.

In relation to such research areas, he published more than 340 papers; three of them received the "best paper award" respectively at IEEE EURODAC'96, IEEE DATE'99 and IEEE FDL'11.He is co-founder and CTO of the EDA company EDALab (www.edalab.it), spin-off of the Università di Verona, focused on networked embedded systems design and tools.From 2012 to 2018 is has been the head of the Department of Computer Science at the Università di Verona, that has been selected by the Italian Ministry of Education, Universities and Research (MIUR) in the 180 "Dipartimenti di Eccellenza 2018-2022" (Departments of Excellence).Under this framework, he is leading the project Computer Engineering for Industry 4.0 (https://www.icelab.di.univr.it/) which is focusing to industrial computer engineering the researches of the entire Department of Computer Science.

Graziano Pravadelli, IEEE senior member, chair of the IFIP 10.5 working group on design and engineering of electronic systems, is full professor of information processing systems at the Computer Science Department of the University of Verona (Italy), where he leads the IoT4Care research group on the design and validation of systems to promote well-being and health of people through technologies related to the Internet of Things. In 2007, he co-founded EDALab s.r.l. (Italy), a SME developing IoT-based monitoring solutions for smart building and wellbeing.His main interests focus on modeling, simulation and semi-formal verification of cyber physical systems, and on the design of IoT-based virtual coaching and remote monitoring platforms for frail people.

Fabian Vargas obtained the PhD Degree in Microelectronics from the Institut National Polytechnique de Grenoble (INPG), France, in 1995. At present, he is Senior Scientist at IHP - Leibniz Institute for High Performance Microelectronics, in Germany. He works in the area of computer systems architecture focusing on test, fault-tolerance and security for critical applications.F. Vargas has served as Technical Committee Member and Guest-Editor in many IEEE-sponsored conferences and journals. He holds 8 BR and international patents, co-authored a book and published over 200 refereed papers.He co-founded the IEEE-Computer Society Latin American Regional Test Technology Technical Council (LA-TTTC) in 1997 and the IEEE Latin American Test Symposium - LATS (former Latin American Test Workshop - LATW) in 2000. F. Vargas received for several times the Meritorious Service Award of the IEEE Computer Society for providing significant services as chair of the IEEE LA-TTTC and LATS. F. Vargas is Senior Member of IEEE and Golden Core Member of the IEEE Computer Society.

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Evolving IoT applications are extremely demanding in terms of storage, energy efficiency as well as intelligence. Todays’ computer architectures fail to meet these requirements due to e.g., memory-processor data transfer bottleneck. Hence, alternative computing architectures are being explored in the light of emerging new device technologies. This talk provides a broad overview of emerging non-volatile devices based computation-in-memory (CIM) architectures, gives its potential in enabling smart local energy efficient computing, and highlights the major challenges ahead. The talk first briefly addresses the need of new computing paradigm with energy efficiency of order of fJ/operation to enable zillions of e.g., edge applications, and shows the limitations of both CMOS scaling and today’s computing architectures. Then it classifies the sate-of-the art computer architectures and highlight how the trends is going toward computation-in-memory (CIM) architectures in order to eliminated and/or significantly reduces the limitations of today’s technologies. The concept of CIM based is discussed and logic and arithmetic circuit designs using such devices and how they enable such architectures are covered. The strong dependency of application domains on the selection of appropriate CIM architecture and its building blocks, as well as the huge potential of CIM (in realizing order of magnitude improvement in terms of energy efficiency) are illustrated based on some case studies.  Thereafter, testing of non-volatile device-based CIM is discussed; it will be demonstrated that traditional approach for fault modelling and test development is incapable to deal with realistic defects in emerging CIM devices, and a new approach called Device Aware Test (DAT) will be covered. Industrial data are presented to show that DAT sensitizes realistic faults as well as new unique defects and faults that can never be caught with the traditional approaches. Future CIM challenges including architectures, design, test, and reliability are highlighted.

Smart production lines can be seen as complex cyber-physical production systems (CPPSs). Their design, implementation, evaluation and testing need some abstraction strategies to focus on the relevant aspects instead of on the low-level details.This talk proposes at first an abstraction methodology, and related tools, starting from the way to build a complete model of the CPPS, based on SysML. There is also the description of protocols (like OPC-UA) to see the CPPS as a service oriented architecture, where IIoT data are collected by an ad-hoc architecture. The model allows the automatic configuration of the smart production line and the generation of its digital-twin, the main simulation infrastructure for its testing.The talk continues through the discussion of which fault models can be used on CPPS and which testing strategies can be thus applied. Non electrical fault models are derived from the electrical equivalence of mechanical, thermal and other models and some fault taxonomieswill be presented.Finally, the way to perform fault simulation on top of digital-twins will complete the talk.

Assertion mining flips the way verification works by extracting formal properties from the actual implementation of the target design and searching for inconsistencies with respect to the initial specification. While this remove the burden of time-consuming and error-prone manual definition, are the mined properties actually human-readable and useful? After reviewing the state of art concerning existing approaches and tools, this talk questions about pros and cons of assertion mining and describes how mined assertions can be exploited, as an effective coverage metrics for functional verification.

Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced IC and electronics since the sixties. Nevertheless, it is well recognized that such scaling has introduced new (and major) reliability challenges to the semiconductor industry. This talk addresses the background mechanisms by which ionizing radiation, electromagnetic emission/immunity (EME/EMI) and aging degrade reliability and lifetime of modern integrated circuits (ICs), the current standards and laboratory test setup for total-ionizing dose (TID), single-event effects (SEEs), EME/EMI and aging on ICs. In the sequence, the current solutions to counteract their combined effects on the reliability of ICs are discussed. Experimental results are described and results analyzed in the light of the combined effects.

Advances in machine learning, notably deep learning, have led computers to match or surpass human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of neural algorithms in conventional "von-Neumann" architectures are several orders of magnitude more area and power expensive than the biological brain.  We believe that exploring this new paradigm of computing necessitates a multi-disciplinary approach: exploration of new learning algorithms inspired from neuroscientific principles, developing network architectures best suited for such algorithms, new hardware techniques to achieve orders of improvement in energy consumption, and nanoscale devices that can closely mimic the “neuronal” and “synaptic” operations leading to a better match between the hardware substrate and the model of computation. In this talk, I will focus on our recent works on neuromorphic learning algorithms and the design of underlying hardware that can lead to quantum improvements in energy efficiency with good accuracy.