24th IEEE Latin-American Test Symposium

Tutorial

"Neuromorphic Computing: Challenges and Solutions for Design and Test – Part 1"

Leticia Maria Bolzani Poehls, RWTH Aachen University – Germany
Jan Moritz Joseph, RWTH Aachen University – Germany

10:30 – 11:00

Coffee-Break

LATS2023 Opening Session

LATS2023 General Co-Chairs

Victor Champac, INAOE - Mexico
YervantZorian, Synopsys - USA

LATS2023 Program Co-Chairs

Leticia Maria Bolzani Poehls, RWTH Aachen University - Germany
Ernesto Sanchez, Politecnicodi Torino - Italy

"Test Aspects of System Health State Monitoring"

Hans-Joachim Wunderlich, Consultant - Germany
Session Chair: Victor Champac, INAOE – Mexico

"Fault Injection Strategies for Reliability Analysis"

Session Chair: Salvador Mir, TIMA – France

A Fast Reliability Analysis of Image Segmentation Neural Networks Exploiting Statistical Fault Injections

Gabriele Gavarini, AnnachiaraRuospoand Ernesto Sanchez
Politecnicodi Torino - Italy

Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning

Esther Goudet ^1,2, Luis Pena Trevino², Lirida Naviner¹, Jean-Marc Daveau² and Philippe Roche^1
1STMicroelectronics – France
²Télécom Paris – France

A Fault Injection Framework for AI Hardware Accelerators

Salvatore Pappalardo¹, Annachiara Ruospo², Ian O’Connor¹, Bastien Deveautour³, Ernesto Sanchez², Alberto Bosio^1
1,³University Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully - France
²Politecnico di Torino–Italy

Coffee-break

Session 2 "Security and Reliability Assessment Using IJTAG"
Session Chair: Erik Larson, Lund University – Sweden (tbc)

SSSN: Secured Streaming Scan Network

Sonali Shukla, Bhavika Ranjeet Kumar and Virendra Singh
ITT Bombay – India

Holistic IJTAG-based External and Internal Fault Monitoring in UAVs

Foisal Ahmed and Maksim Jenihhin
Tallinn University of Technology – Estonia

"Co-optimization of security and accessibility to on-chip instruments"

Erik Larsson, Lund University – Sweden
Session Chair: Maksim Jenihhin, Tallinn University of Technology - Estonia

Lunch

"A New Era for Test: From the Manufacturing Floor to the
Field"

Shawn Blanton, Carnegie Mellon University – USA
Session Chair: Hans-Joachim Wunderlich, Consult – Germany (tbc)

Special Session“AMS-RS Testing”
Organized by Florence Azaïs, LIRMM– France

High-frequency Sinusoidal Signal Generation using harmonic cancellation

Ankush Mamgain¹, Salvador Mir¹, Jai Narayan Tripathi², Manuel J. Barragan^1
1University Grenoble Alpes, CNRS, Grenoble INP, TIMA- France
²Indian Institute of Technology Jodhpur - India

Low-cost digital solution for production test of ZigBee transmitters

Thibault Vayssade, Florence Azaïs, Laurent Latorre, François Lefèvre
LIRMM, University Montpellier / CNRS – France
NXP Semiconductors - France

On-chip self-referenced jitter estimation with sub-picosecond resolution

Manasa Madhvaraj, Salvador Mir, Manuel J. Barragan
University Grenoble Alpes, CNRS, Grenoble INP, TIMA- France

"Functional Testing techniques: a short overview encompassing Software-Based Self-Test, Burn-In Functional Stress/Test and System Level Test"

Paolo Bernardi, Politecnicodi Torino - Italy
Session Chair: Shawn Blanton, Carnegie Mellon University – USA (tbc)

Coffee-break

"Error Resilient Neuromorphic Systems Using Embedded Predictive Neuron Checks"

Abhijit Chatterjee, Georgia Institute of Technology - USA
Session Chair: Ernesto Sanchez, Politecnico di Torino – Italy

Invited Papers, Posters & Late Contributions

(Invited Paper) X-FLIM: A Holistic Fault Injection Platform for Neuromorphic
Hardware

Felix Staudigl¹, Thorben Fetz¹, Rebecca Pelke¹, Dominik Sisejkovic³, Jan Moritz Joseph¹, Leticia Maria Bolzani Poehls², Rainer Leupers^1
1ICE, RWTH Aachen University, Germany
²IDS, RWTH Aachen University, Germany
³Corporate Research Robert Bosch GmbH, Germany

(Late Contribution) Low cost external serial interface watchdog for SoCs and
FPGAs automatic characterization tests

Paolo Bernardi, Gabriele Filipponi, Tommaso Foscale and Giorgio Insinga
Politecnico di Torino, Italy

(Late Contribution) Near-infrared spectroscopy for real-time imaging of human brain function

P. Mabil. Espinosa*, J. Martinez-Castillo*, S. Salas Rodriguez, E. Delgado Alvarado, M. Herrera González and J.J. Espinoza Maza
Micro and Nanotechnology Research Center, Universidad Veracruzana

(Poster) LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error

Pooja Choudhary^{1, 2}, Lava Bhargava², Masahiro Fujita³ and Virendra Singh^4
1Malaviya National Institute of Technology - India
²Swami Keshvanand Institute of Technology, Management and Gramothan - India
³University of Tokyo - Japan
⁴ITT Bombay – India

(Poster) Blockchain Applied in Decentralization of Ground Stations to mission of Nanosatellites

Jose Edilson Silva Filho, Jarbas Aryel Nunes da Silveira and Cesar Augusto Missio Marcon
University of Ceará, Brazil

Welcome Cocktail

Keynote Talk

"Silicon Lifecycle Management: Trends & Solutions"

Yervant Zorian, Synposys – USA
Session Chair: Adit Singh, Auburn Univeristy – USA (invited)

Social Event

Gala Dinner

Embedded Tutorial

Silent Error Corruption: The New Reliability and Test Challenge"

Adit Singh, Auburn University - USA
Session Chair: Yervant Zorian, Synopsys – USA (invited)

Session 3 "Transient Faults and Fault Tolerance"
Session Chair: Hector Villacorta, Semtech – Mexico

Effect of Vth shifting in CMOS Transistors under radiation conditions when applying OBT: A case study

Pablo Antonio Petrashin¹, Walter Lancioni¹, Fortunato Dualibe², Juan Castagnola¹ and Agustin Laprovitta^1
1Universida Católica de Córdoba - Argentina
²Facultépolytechnique de Mons – Belgium

Fault Tolerant architecture design of a CubeSat Command and Data Handling system

Christo A. Lara¹, Maximiliano Fragoso¹, Luis Manuel Juárez¹, Leonardo Barboni², Rigoberto Reyes³, Ricardo Vazquez³, Julio Pérez Acle² and Saúl de la Rosa^1
1UNAM – Mexico
²Facultad de Ingeniería, Udelar - Uruguay
³Agencia Espacial Mexicana – Mexico

Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs

Josie Esteban Rodriguez Condia¹, Juan David Guerrero Balaguera¹, Edwar J. Patino Nunez², Robert Limas Sierra¹ and Matteo Sonza Reorda^1
1Politecnico di Torino – Italy
²UPTC – Colombia

Visionary Talk

"Rethinking Computing with Neuro-inspired Learning:
Algorithms to Hardware"

Kaushik Roy, Purdue University – USA
Session Chair: Abhijit Chatterjee, Georgia Institute of Technology – USA

Coffee-break

Invited Talk

"Analyzing Side-Channel Attack Vulnerabilities at RTL"

Panel

"Silent Data Corruption: Challenges and Solutions"

Organized by YervantZorian, Synposys – USA

12:30 – 14:30

Lunch

Invited Talk

"Testing for Smart Production Lines"

Franco Fummi, Universitiy of Verona - Italy
Session Chair: TBD

Session 4 "Defect and Fault Modeling"
Session Chair: Thiago Santos Copetti, RWTH Aachen University - Germany

A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates Make with SADP and Gate Replacement Process

Victor Champac¹, Freddy Forero¹, Michel Renovell Renovell² and Leonardo Miceli^1
1INAOE – Mexico
²LIRMM – France

Abstractions for Modeling the Effects of Wall Surface Roughness in Silicon Photonic Microring Resonators

Pratishtha Agnihotri, Lawrence Schlitt, Priyank Kalla and Steve Blair
University of Utah – USA

Coffee-Break

Session 5 "Test Strategies"
Session Chair: Gustavo Rifka, Mexico (invited)

On the integration and hardening of Software Test Libraries in Real-Time Operating Systems

Francesco Angion², Paolo Bernardi², Riccardo Cantoro², Nicola diGruttola Giardino², Davide Piumatti², Matteo Sonza Reorda², Davide Appello¹ and Vincenzo Tancorre^1
1ST Microelectronics – Italy
²Politecnico di Torino - Italy

Feature selection for cost reduction in MCU performance screening

Nicolò Bellarmino, Riccardo Cantoro¹, Martin Huch², Tobias Kilian²,³, Ulf Schlichtmann² and Giovanni Squillero^1
1Politecnico di Torino – Italy
²Infineon Technologies AG – Germany
³Technical University of Munich – Germany

Evaluating a New RRAM Manufacturing Test Strategy

Thiago Santos Copetti¹, Andrea Castelnuovo², Tobias Gemmeke¹, Leticia Bolzani Poehls^1
1RWTH Aachen University – Germany
²NXP Semiconductors – Germany

LATS2023 Closing Session