24th IEEE Latin-American Test Symposium

Veracruz, Mexico, 21st - 24th March 2023


CALL FOR PAPERS Proceedings LATS2023

Preliminary Technical Program

(Updated March 14, 2023)


Tuesday March 21st, 2023 (Student Activities)

09:00 – 10:30


"Neuromorphic Computing: Challenges and Solutions for Design and Test – Part 1"

Leticia Maria Bolzani Poehls, RWTH Aachen University – Germany
Jan Moritz Joseph, RWTH Aachen University – Germany

10:30 – 11:00


11:00 – 12:30


"Neuromorphic Computing: Challenges and Solutions for Design and Test – Part 2"

Leticia Maria Bolzani Poehls, RWTH Aachen University – Germany
Jan Moritz Joseph, RWTH Aachen University – Germany

12:30 – 14:00


14:00 – 15:00


"Assessing the ANN reliability: Issues, Strategies and Opportunities"

Ernesto Sanchez, Politecnicodi Torino – Italy

15:00 – 15:30


15:30 – 16:30
McCluskey PhD Contest

Wednesday March 22nd, 2023

08:30 – 09:00

LATS2023 Opening Session

LATS2023 General Co-Chairs

Victor Champac, INAOE - Mexico
YervantZorian, Synopsys - USA

LATS2023 Program Co-Chairs

Leticia Maria Bolzani Poehls, RWTH Aachen University - Germany
Ernesto Sanchez, Politecnicodi Torino - Italy

09:00 – 09:35
Keynote Talk
"Test Aspects of System Health State Monitoring"

Hans-Joachim Wunderlich, Consultant - Germany
Session Chair: Victor Champac, INAOE – Mexico

09:35 – 10:35
Session 1
"Fault Injection Strategies for Reliability Analysis"

Session Chair: Salvador Mir, TIMA – France

A Fast Reliability Analysis of Image Segmentation Neural Networks Exploiting Statistical Fault Injections

Gabriele Gavarini, AnnachiaraRuospoand Ernesto Sanchez
Politecnicodi Torino - Italy

Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning

Esther Goudet 1,2, Luis Pena Trevino2, Lirida Naviner1, Jean-Marc Daveau2 and Philippe Roche1
1STMicroelectronics – France
2Télécom Paris – France

A Fault Injection Framework for AI Hardware Accelerators

Salvatore Pappalardo1, Annachiara Ruospo2, Ian O’Connor1, Bastien Deveautour3, Ernesto Sanchez2, Alberto Bosio1
1,3University Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully - France
2Politecnico di Torino–Italy

10:35 – 11:00


11:00- 11:40

Session 2 "Security and Reliability Assessment Using IJTAG"
Session Chair: Erik Larson, Lund University – Sweden (tbc)

SSSN: Secured Streaming Scan Network

Sonali Shukla, Bhavika Ranjeet Kumar and Virendra Singh
ITT Bombay – India

Holistic IJTAG-based External and Internal Fault Monitoring in UAVs

Foisal Ahmed and Maksim Jenihhin
Tallinn University of Technology – Estonia

11:40 – 12:10
Embedded Tutorial
"Co-optimization of security and accessibility to on-chip instruments"

Erik Larsson, Lund University – Sweden
Session Chair: Maksim Jenihhin, Tallinn University of Technology - Estonia

12:10 – 14:00


14:00 – 14:30
Keynote Talk
"A New Era for Test: From the Manufacturing Floor to the

Shawn Blanton, Carnegie Mellon University – USA
Session Chair: Hans-Joachim Wunderlich, Consult – Germany (tbc)

14:30 – 15:30

Special Session“AMS-RS Testing”
Organized by Florence Azaïs, LIRMM– France

High-frequency Sinusoidal Signal Generation using harmonic cancellation

Ankush Mamgain1, Salvador Mir1, Jai Narayan Tripathi2, Manuel J. Barragan1
1University Grenoble Alpes, CNRS, Grenoble INP, TIMA- France
2Indian Institute of Technology Jodhpur - India

Low-cost digital solution for production test of ZigBee transmitters

Thibault Vayssade, Florence Azaïs, Laurent Latorre, François Lefèvre
LIRMM, University Montpellier / CNRS – France
NXP Semiconductors - France

On-chip self-referenced jitter estimation with sub-picosecond resolution

Manasa Madhvaraj, Salvador Mir, Manuel J. Barragan
University Grenoble Alpes, CNRS, Grenoble INP, TIMA- France

15:30 – 16:00
Embedded Tutorial
"Functional Testing techniques: a short overview encompassing Software-Based Self-Test, Burn-In Functional Stress/Test and System Level Test"

Paolo Bernardi, Politecnicodi Torino - Italy
Session Chair: Shawn Blanton, Carnegie Mellon University – USA (tbc)

16:00 – 16:15


16:15 – 16:45
Keynote Talk
"Error Resilient Neuromorphic Systems Using Embedded Predictive Neuron Checks"

Abhijit Chatterjee, Georgia Institute of Technology - USA
Session Chair: Ernesto Sanchez, Politecnico di Torino – Italy

16:45 – 17:30

Invited Papers, Posters & Late Contributions

(Invited Paper) X-FLIM: A Holistic Fault Injection Platform for Neuromorphic

Felix Staudigl1, Thorben Fetz1, Rebecca Pelke1, Dominik Sisejkovic3, Jan Moritz Joseph1, Leticia Maria Bolzani Poehls2, Rainer Leupers1
1ICE, RWTH Aachen University, Germany
2IDS, RWTH Aachen University, Germany
3Corporate Research Robert Bosch GmbH, Germany

(Late Contribution) Low cost external serial interface watchdog for SoCs and
FPGAs automatic characterization tests

Paolo Bernardi, Gabriele Filipponi, Tommaso Foscale and Giorgio Insinga
Politecnico di Torino, Italy

(Late Contribution) Near-infrared spectroscopy for real-time imaging of human brain function

P. Mabil. Espinosa*, J. Martinez-Castillo*, S. Salas Rodriguez, E. Delgado Alvarado, M. Herrera González and J.J. Espinoza Maza
Micro and Nanotechnology Research Center, Universidad Veracruzana

(Poster) LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error

Pooja Choudhary1, 2, Lava Bhargava2, Masahiro Fujita3 and Virendra Singh4
1Malaviya National Institute of Technology - India
2Swami Keshvanand Institute of Technology, Management and Gramothan - India
3University of Tokyo - Japan
4ITT Bombay – India

(Poster) Blockchain Applied in Decentralization of Ground Stations to mission of Nanosatellites

Jose Edilson Silva Filho, Jarbas Aryel Nunes da Silveira and Cesar Augusto Missio Marcon
University of Ceará, Brazil

From 19:00

Welcome Cocktail

Thursday March 23rd, 2023

08:30– 09:00

Keynote Talk

"Silicon Lifecycle Management: Trends & Solutions"

Yervant Zorian, Synposys – USA
Session Chair: Adit Singh, Auburn Univeristy – USA (invited)

09:30 – 19:00

Social Event

From 20:00

Gala Dinner

Friday March 24th, 2023

09:00 – 09:30

Embedded Tutorial

Silent Error Corruption: The New Reliability and Test Challenge"

Adit Singh, Auburn University - USA
Session Chair: Yervant Zorian, Synopsys – USA (invited)

09:30 – 10:30

Session 3 "Transient Faults and Fault Tolerance"
Session Chair: Hector Villacorta, Semtech – Mexico

Effect of Vth shifting in CMOS Transistors under radiation conditions when applying OBT: A case study

Pablo Antonio Petrashin1, Walter Lancioni1, Fortunato Dualibe2, Juan Castagnola1 and Agustin Laprovitta1
1Universida Católica de Córdoba - Argentina
2Facultépolytechnique de Mons – Belgium

Fault Tolerant architecture design of a CubeSat Command and Data Handling system

Christo A. Lara1, Maximiliano Fragoso1, Luis Manuel Juárez1, Leonardo Barboni2, Rigoberto Reyes3, Ricardo Vazquez3, Julio Pérez Acle2 and Saúl de la Rosa1
1UNAM – Mexico
2Facultad de Ingeniería, Udelar - Uruguay
3Agencia Espacial Mexicana – Mexico

Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs

Josie Esteban Rodriguez Condia1, Juan David Guerrero Balaguera1, Edwar J. Patino Nunez2, Robert Limas Sierra1 and Matteo Sonza Reorda1
1Politecnico di Torino – Italy
2UPTC – Colombia

10:30 – 11:00

Visionary Talk

"Rethinking Computing with Neuro-inspired Learning:
Algorithms to Hardware"

Kaushik Roy, Purdue University – USA
Session Chair: Abhijit Chatterjee, Georgia Institute of Technology – USA

11:00 – 11:15


11:15 – 11:45

Invited Talk

"Analyzing Side-Channel Attack Vulnerabilities at RTL"
Maksim Jenihhin, Tallinn University of Technology, Estonia
Session Chair: Paolo Bernardi, Politecnico di Torino – Italy
11:45 – 12:30


"Silent Data Corruption: Challenges and Solutions"

Organized by YervantZorian, Synposys – USA

12:30 – 14:30


14:30 – 15:00

Invited Talk

"Testing for Smart Production Lines"

Franco Fummi, Universitiy of Verona - Italy
Session Chair: TBD

15:00 – 15:40

Session 4 "Defect and Fault Modeling"
Session Chair: Thiago Santos Copetti, RWTH Aachen University - Germany

A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates Make with SADP and Gate Replacement Process

Victor Champac1, Freddy Forero1, Michel Renovell Renovell2 and Leonardo Miceli1
1INAOE – Mexico
2LIRMM – France

Abstractions for Modeling the Effects of Wall Surface Roughness in Silicon Photonic Microring Resonators

Pratishtha Agnihotri, Lawrence Schlitt, Priyank Kalla and Steve Blair
University of Utah – USA

15:40 – 16:00


16:00 – 17:00

Session 5 "Test Strategies"
Session Chair: Gustavo Rifka, Mexico (invited)

On the integration and hardening of Software Test Libraries in Real-Time Operating Systems

Francesco Angion2, Paolo Bernardi2, Riccardo Cantoro2, Nicola diGruttola Giardino2, Davide Piumatti2, Matteo Sonza Reorda2, Davide Appello1 and Vincenzo Tancorre1
1ST Microelectronics – Italy
2Politecnico di Torino - Italy

Feature selection for cost reduction in MCU performance screening

Nicolò Bellarmino, Riccardo Cantoro1, Martin Huch2, Tobias Kilian2,3, Ulf Schlichtmann2 and Giovanni Squillero1
1Politecnico di Torino – Italy
2Infineon Technologies AG – Germany
3Technical University of Munich – Germany

Evaluating a New RRAM Manufacturing Test Strategy

Thiago Santos Copetti1, Andrea Castelnuovo2, Tobias Gemmeke1, Leticia Bolzani Poehls1
1RWTH Aachen University – Germany
2NXP Semiconductors – Germany


17:00 – 17:30
LATS2023 Closing Session